EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 545

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
July 2005
×2×4
×2×8
×4×16
×2×16
×2×4
×2×8
×4×16
×2×16
×2×4
×2×8
×4×16
×2×16
M512 Mode
Table 5–18. Address Counters for SERDES Bypass LVDS Receiver
Table 5–19. Address Counters for SERDES Bypass LVDS Transmitter
Table 5–20. Address & Counter Width
M512 Mode
M512 Mode
Write Counter
Width
Deserialization
Deserialization
4
5
6
5
Factor
Factor
16
16
4
8
8
4
8
8
For the transmitter, the read counter is the fast counter and the write
counter is the slow counter. For the receiver, the write counter is the fast
counter and the read counter is the slow counter.
provide the address counter configurations for the transmitter and the
receiver, respectively.
In different M512 memory configurations, the counter width is smaller
than the address width, so you must ground some of the most significant
address bits.
width, and the number of bits to be grounded.
Read Counter
Width
3
3
3
3
Width
Width
Write Up-Counter
Write Up-Counter
(Fast Counter)
(Fast Counter)
4
5
5
6
4
5
5
6
Table 5–20
Write Address
Width
High-Speed Differential I/O Interfaces in Stratix Devices
Starts at
Starts at
8
8
7
8
0
0
0
0
0
0
0
0
summarizes the address width, the counter
Read Address
Width
Width
Read Up-Counter
Read Up-Counter
(Slow Counter)
(Slow Counter)
Width
3
3
3
3
3
3
3
3
7
6
5
5
Stratix Device Handbook, Volume 2
Starts at
Starts at
Write Address Read Address
2
2
2
2
2
2
2
2
Number of Grounded Bits
Tables 5–18
4
3
1
3
Invalid Initial Cycles
Invalid Initial Cycles
Write
Write
12
24
24
48
2
2
2
2
and
Read
Read
4
3
2
2
5–19
16
6
6
6
6
4
8
8
5–73