EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 242
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 242 of 864
- Download datasheet (11Mb)
Timing Model
4–62
Stratix Device Handbook, Volume 1
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V GTL
2.5-V GTL
3.3-V GTL+
2.5-V GTL+
3.3-V SSTL-3 Class II
Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 1 of 2)
Notes
I/O Standard
(1), (2),
(3)
R
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
Notes to
(1)
(2)
–
–
–
–
–
–
–
–
–
–
–
–
–
UP
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
V
CCINT
R
Figure
–
–
–
–
–
–
–
–
–
–
–
–
–
DN
is 1.42-V unless otherwise specified.
4–7:
Loading and Termination
R
25
0
0
0
0
0
0
0
0
0
0
0
0
S
VCCIO
Output
Buffer
GND
25
25
25
25
25
R
–
–
–
–
–
–
–
–
T
Single-Ended Outputs
OUTPUT
2.950
2.370
1.650
1.400
2.950
2.370
1.650
1.400
2.950
2.370
2.950
2.370
2.950
V
(V)
CCIO
V
MEAS
VCCIO
GND
2.95
2.37
1.65
1.40
2.95
2.37
1.65
1.40
1.14
1.14
1.35
1.35
1.25
VTT
(V)
R
R
DN
UP
R
S
GND
V
TT
(pF)
C
R
10
10
10
10
10
10
10
10
30
30
30
30
30
C
L
T
L
Altera Corporation
Measurement
January 2006
V
1.500
1.200
0.880
0.750
1.500
1.200
0.880
0.750
0.740
0.740
0.880
0.880
1.250
Point
MEAS
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