PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 85

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
5.3
The data cache serves only the DSPCPU and is con-
trolled by two memory units that execute the load and
store operations issued by the DSPCPU. The following
sections describe the data cache and its operation;
Table 5-3
easy reference.
Table 5-3. Summary of data cache characteristics
Figure 5-3. Format of the DC_PARAMS register.
Figure 5-4. Data cache address partitioning.
Cache size
Cache associativity
Block size
Valid bits
Dirty bits
Miss transfer order
Replacement poli-
cies
Endianness
Ports
Alignment
Partial word opera-
tions
Operation latency
Coherency enforce-
ment
Cache locking
Non-cacheable
region
Data Cache Address
MMIO_BASE
Characteristic
0x10 001C
offset:
DATA CACHE
summarizes the important characteristics for
DC_PARAMS (r/o)
16 KB
8-way set-associative
64 bytes
One valid bit per 64-byte block
One dirty bit per 64-byte block
Miss transfers begin with the critical
word first
Copyback, allocate on write, hierarchical
LRU
Either little- or big-endian, determined
by PCSW bit
The cache is quasi dual ported; two
accesses can proceed concurrently if
they reference different banks (deter-
mined by bits [4:2] of the computed
addresses)
Access must be naturally aligned (32-bit
words on 32-bit boundaries, 16-bit half-
words on 16-bit boundaries); the appro-
priate number of LSBs of un-naturally
aligned addresses are set to zero.
For misaligned stores, PCSW.MSE is
asserted to generate an exception
The cache implements 8-bit and 16-bit
accesses with the same performance as
32-bit accesses
Three cycles for both load and store
operations
Software uses special operations to
enforce cache coherency
Up to 1/2 (four out of 8 blocks of each
set) of the cache contents can be
locked; granularity is 64-byte
One non-cacheable aperture in the
DRAM address space is supported.
31
PNX1300 Implementation
31
27
Tag
23
BLOCKSIZE
5.3.1
The PNX1300 data cache is 16 KB in size with a 64-byte
block size. Thus, it contains 256 blocks each with its own
address tag. The cache is 8-way set-associative, so
there are 32 sets, each containing 8 tags. A single valid
bit is associated with a block, so each block and associ-
ated address tag is either entirely valid in the cache or in-
valid. On a cache miss, 64 bytes are read from SDRAM
to make the entire block valid.
Each block also contains a dirty bit, which is set whenev-
er a write to the block occurs. Each set contains 10 bits
to support the hierarchical LRU replacement policy.
The geometry of the data cache is available to software
by reading the MMIO register DC_PARAMS.
shows the format of the DC_PARAMS register;
Table 5-4
associativity, and number of sets gives the total cache
size (16 KB in this case).
Table 5-4. DC_PARAMS field values
5.3.2
PNX1300 data addresses are mapped onto the data
cache storage structure as shown in
address is partitioned into four fields as described in
Table
Table 5-5. Data address field partitioning
PRELIMINARY SPECIFICATION
BLOCK SIZE
ASSOCIATIVITY
NUMBER_OF_SETS
Field
Word
Byte
Set
Tag
19
5-5.
Address
31..11
10..6
Bits
General Cache Parameters
Address Mapping
lists its field values. The product of block size,
1..0
5..2
Field Name
ASSOCIATIVITY
15
Byte offset within a word for byte or half-
word accesses
Selects one of the words in a set (one of
16 words in the case of PNX1300)
Selects one of the sets in the cache (one
of 32 in the case of PNX1300)
Compared against address tags of set
members
11
10
11
Set
6
Purpose
NUMBER_OF_SETS
Cache Architecture
5
7
Figure
Word
2
5-4. A data
3
Figure 5-3
Value
1
Byte
64
32
8
0
0
5-3