PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 393
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PNX1301EH
Manufacturer Part Number
PNX1301EH
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1301EH.pdf
(548 pages)
Specifications of PNX1301EH
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ifloatrzflags
SYNTAX
FUNCTION
DESCRIPTION
integer in rsrc1 to a single-precision IEEE floating-point value, and an integer bit vector representing the computed
exception flags is written into rdest. The bit vector stored in rdest has the same format as the IEEE exception bits in
the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is performed toward zero;
the IEEE rounding mode bits in PCSW are ignored.
controls the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not
changed.
EXAMPLES
A-95
r30 = 3
r40 = 0xffffffff (-1)
r10 = 0, r50 = 0xfffffffd
r20 = 1, r50 = 0xfffffffd
r60 = 0x7fffffff (2147483647)
r70 = 0x80000000 (-2147483648)
r80 = 0x7ffffff1 (2147483633)
The
The
[ IF rguard ] ifloatrzflags rsrc1 → rdest
if rguard then
rdest ← ieee_flags((float) ((long)rsrc1))
ifloatrzflags
ifloatrzflags
31
0
Initial Values
PRELIMINARY SPECIFICATION
operation computes the IEEE exceptions that would result from converting the signed
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB
ifloatrzflags r30 → r100
ifloatrzflags r40 → r105
IF r10 ifloatrzflags r50 → r110
IF r20 ifloatrzflags r50 → r115
ifloatrzflags r60 → r117
ifloatrzflags r70 → r120
ifloatrzflags r80 → r122
IEEE status flags from convert signed integer to
floating-point with rounding toward zero
Operation
7
0
OFZ
6
IFZ
5
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ufloatflags ufloatrzflags
r100 ← 0
r105 ← 0
no change, since guard is false
r115 ← 0
r117 ← 0x02 (INX)
r120 ← 0
r122 ← 0x02 (INX)
OVF
ifloatrz ifloatflags
3
Philips Semiconductors
UNF
ATTRIBUTES
2
SEE ALSO
Result
INX
1
DBZ
0
1, 4
falu
118
No
—
1
3
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