PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 250

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
cates the microactivity of the I
ues and their meanings are presented in
DIRECTION status bit indicates if the
transmit or receive mode.
• if DIRECTION = 0 then I
• if DIRECTION = 1 then I
The RBC bitfield indicates the remaining bytecount for an
I
as a read-only ‘shadow register’ for the IIC_AR.COUNT
bitfield. During
the remaining bytecount. To avoid corrupting an
transfer, the DSPCPU must refrain from writing to the
IIC_AR.COUNT bitfield until a message is complete.
Completion is indicated by the RBC bitfield decrementing
to zero.
16.4.4
The I
quired for enabling
enable and clear interrupt sources which normally occur
during
scribed in the section on the IIC_SR register are enabled
and cleared through the IIC_CR register. The enable bit-
fields are:
16-4
2
27:26
21:6
C
Bits
31
30
29
28
25
24
23
22
10
transfer in progress. The IIC_SR.RBC bitfield serves
2
C control register contains control information re-
I
SW_MODE_EN 0 (power-on/reset default) - Normal
2
CLRSDNACKI
SANACK_IEN
SDNACK_IEN
CLRSANACKI
C
Field Name
Reserved1
Reserved2
IIC_CR Register
GD_IEN
CLRGDI
CLRFI
operation. The four interrupt sources de-
F_IEN
Table 16-7. IIC_CR Register
I
2
C
I
transfer, the RBC bitfield will reflect
2
C
PRELIMINARY SPECIFICATION
transfers. This register is used to
Enable for normal transfer complete
interrupt
Enable for IIC_DR data service
request interrupt
Enable for slave address not
acknowledged interrupt
Enable for slave data not acknowl-
edged interrupt. An addressed slave
receiver has refused to accept the
last byte transmitted to it
Always write ‘0’s to these bits.
(See Note1)
Clear bit for the GDI interrupt in the
IIC_SR register. Writing a ‘1’ to this
bit clears the GDI interrupt
Clear bit for the FI interrupt in the
IIC_SR register. Writing a ‘1’ to this
bit clears the FI interrupt
Clear bit for the SANACKI interrupt
in the IIC_SR register. Writing a ‘1’ to
this bit clears the SANACKI interrupt.
Clear bit for the SDNACKI interrupt
in the IIC_SR register. Writing a ‘1’ to
this bit clears the SDNACKI interrupt.
Always write ‘0’s to these bits.
(See Note1)
I2C hardware operating mode.
1 - Enable software operating mode.
The I
by user writes to the ‘sda_out’ and
‘scl_out’ register bits.
2
2
2
C is a transmitter.
C is a receiver.
C pins are entirely controlled
2
C interface. The field val-
Definition
I
2
C
Table 16-5
interface is in
The
I
2
C
• GD_IEN — Enable for normal transfer complete
• F_IEN — Enable for IIC_DR data service request
• SANACK_IEN — Enable for slave address not
• SDNACK_IEN — Enable for slave data not acknowl-
In addition to the interrupt enable bits, the IIC_CR con-
tains interrupt clear bits associated with each of the inter-
rupt sources in the IIC_SR register. These IIC_CR inter-
rupt clear bits are defined as:
• CLRGDI — Clear bit for the GDI interrupt in the
• CLRFI — Clear bit for the FI interrupt in the IIC_SR
• CLRSANACKI — Clear bit for the SANACKI inter-
• CLRSDNACKI — Clear bit for the SDNACKI inter-
The remaining bitfield of the IIC_CR register is:
• ENABLE — Master enable for I
Bits
5:2
7
6
1
0
interrupt.
interrupt.
acknowledged interrupt. This is an error interrupt.
edged interrupt. An addressed slave receiver has
refused to accept the last byte transmitted to it. This
is handled as an error interrupt.
IIC_SR register. Writing a ‘1’ to this bit clears the GDI
interrupt.
register. Writing a ‘1’ to this bit clears the FI interrupt.
rupt in the IIC_SR register. Writing a ‘1’ to this bit
clears the SANACKI interrupt.
rupt in the IIC_SR register. Writing a ‘1’ to this bit
clears the SDNACKI interrupt.
ENABLE must be set equal to ‘1’ to transfer any bits
from the I
ENABLE bit effectively resets the entire I
including all status and interrupt flag bits. A transfer
in progress is aborted and the byte currently trans-
ferred is lost.
Note: For writes, Reserved1, 2, 3 and 4 bitfields
MUST always be written with ‘0’s.
Table 16-7. IIC_CR Register (Continued)
Field Name
Reserved3
Reserved4
SDA_OUT
SCL_OUT
ENABLE
2
C interface block. Writing a ‘0’ to the
Enabled by sw_mode_en. This bit is
used by sw to manually control the
external I
ity is:
1 = SDA pad pulled low
0 = SDA pad left open drain
Enabled by sw_mode_en. This bit is
used by sw to manually control the
external I
ity is:
1 = SCL pad pulled low
0 = SCL pad left open drain
Always write ‘0’s to these bits.
(See Note1)
Always write ‘0’s to these bits.
(See Note1)
I
2
C serial interface enable
Philips Semiconductors
2
2
C SDA data pin. Bit polar-
C SCL clock pin. Bit polar-
Definition
2
C serial interface.
2
C interface,