PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 267

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

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JTAG Functional Specification
18.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The IEEE 1149.1 (JTAG) standard can be used for vari-
ous purposes including testing connections between in-
tegrated circuits on board level, controlling the testing of
the internal structures of the integrated circuits, and mon-
itoring and communicating with a running system.
The JTAG standard defines on-chip test logic, four or five
dedicated pins collectively called the Test Access Port
(TAP) and a TAP controller.
The JTAG standard defines instructions that must al-
ways be implemented by a TAP controller in order to
guarantee correct behavior on board level. Apart from
mandatory instructions, the standard also allows user-
defined and private instructions. In PNX1300, user de-
fined and private instructions exist for debug purposes
and for production test. For debug there is communica-
tion between a debug monitor running on the PNX1300
DSPCPU and a debugger front-end running on a host
computer. This will be explained in chapter
18.2
The Test Access Port includes three or four dedicated in-
put pins and one output pin:
• TCK (Test Clock)
• TMS (Test Mode Select)
• TDI (Test Data In)
• TRST (Test Reset, optional!)
• TDO (Test Data Out)
TRST is not present on PNX1300.
TCK provides the clock for test logic required by the stan-
dard. TCK is asynchronous to the system clock. Stored
state devices in JTAG controller must retain their state
indefinitely when TCK is stopped at 0 or 1.
The signal received at TMS is decoded by the TAP con-
troller to control test functions. The test logic is required
to sample TMS at the rising edge of TCK.
Serial test instructions and test data are received at TDI.
The TDI signal is required to be sampled at the rising
edge of TCK. When test data is shifted from TDI to TDO,
the data must appear without inversion at TDO after a
number of rising and falling edges of TCK determined by
the length of the instruction or test data register selected.
OVERVIEW
TEST ACCESS PORT (TAP)
by Renga Sundararajan, Hans Bouwmeester and Frank Bouwman
Section 18.3
TDO is the serial output for test instructions and data
from the TAP controller. Changes in the state of TDO
must occur at the falling edge of TCK. This is because
devices connected to TDO are required to sample TDO
at the rising edge of TCK. The TDO driver must be in an
inactive state (i.e., TDO line HIghZ) except when data
scanning is in progress.
18.2.1
The TAP controller is a finite state machine; it synchro-
nously responds to changes in TCK and TMS signals.
The TAP instructions and data are serially scanned into
the TAP controller’s instruction and data registers via the
common input line TDI. The TMS signal tells the TAP
controller to select either the TAP instruction register or
a TAP data register as the destination for serial input
from the common line TDI. An instruction scanned into
the instruction register selects a data register to be con-
nected between TDI and TDO and hence to be the des-
tination for serial data input.
TAP controller state changes are determined by the TMS
signal. The states are used for scanning in/out TAP in-
struction and data, updating instruction and data regis-
ters, and for executing instructions.
The controller state diagram
rate states for ‘capture’, ‘shift’ and ‘update’ of data and in-
structions. The reason for separate states is to leave the
contents of a data register or an instruction register un-
disturbed until serial scan-in is finished and the update
state is entered. By separating the shift and update
states, the contents of a register (the parallel stage) is not
affected during scan in/out.
The TAP controller must be in Test Logic Reset state af-
ter power-up. It remains in that state as long as TMS is
held at ‘1’. It transitions to Run-Test/Idle state when TMS
= ‘0’. The Run-Test/Idle state is an idle state of the con-
troller in between scanning in/out an instruction/data reg-
ister. The ‘Run-Test’ part of the name refers to start of
built-in tests. The “Idle” part of the name refers to all other
cases. Note that there are two similar sub-structures in
the state diagram, one for scanning in an instruction and
another for scanning in data. To scan in/out a data regis-
ter, one has to scan in an instruction first.
An instruction or data register must have at least two
stages, a shift register stage and a parallel input/output
stage. When an n-bit data register is to be ‘read’, the reg-
ister is selected by an instruction. The registers contents
are ‘captured’ first (loaded in parallel into shift register
stage), n bits are shifted in and at the same time n bits
PRELIMINARY SPECIFICATION
TAP Controller
(Figure
Chapter 18
18-1) shows sepa-
18-1