PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 513
PNX1301EH
Manufacturer Part Number
PNX1301EH
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1301EH.pdf
(548 pages)
Specifications of PNX1301EH
Lead Free Status / RoHS Status
Not Compliant
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Part Number
Manufacturer
Quantity
Price
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Part Number:
PNX1301EH
Manufacturer:
MARVELL
Quantity:
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Company:
Part Number:
PNX1301EH,557
Manufacturer:
NXP Semiconductors
Quantity:
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Part Number:
PNX1301EH/G(ROHS)
Manufacturer:
PHILIPS/飞利浦
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20 000
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Philips Semiconductors
IC_LOCK_SIZE
PLL_RATIOS
BLOCK_POWER_DOWN
VI_STATUS
VI_CTL
VI_CLOCK
VI_CAP_START
VI_CAP_SIZE
VI_BASE1
VI_Y_BASE_ADR
VI_BASE2
VI_U_BASE_ADR
VI_SIZE
VI_V_BASE_ADR
VI_UV_DELTA
VI_Y_DELTA
VO_STATUS
VO_CTL
VO_CLOCK
VO_FRAME
VO_FIELD
VO_LINE
VO_IMAGE
VO_YTHR
VO_OLSTART
VO_OLHW
VO_YADD
VO_UADD
VO_VADD
VO_OLADD
VO_VUF
VO_YOLF
EVO_CTL
EVO_MASK
EVO_CLIP
EVO_KEY
EVO_SLVDLY
AI_STATUS
AI_CTL
AI_SERIAL
AI_FRAMING
MMIO Register Name
10 0218
10 0300
10 3428
10 1400
10 1404
10 1408
10 1410
10 1414
10 1418
10 1420
10 1424
10 1800
10 1804
10 1808
10 1810
10 1814
10 1818
10 1820
10 1824
10 1828
10 1830
10 1834
10 1838
10 1840
10 1844
10 1848
10 1850
(in hex)
10 140c
10 141c
10 180c
10 181c
10 182c
10 183c
10 184c
10 1c00
10 1c04
10 1c08
10 1c0c
Offset
DSPCPU
R/W
R/—
R/W
R/—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/—
R/W
R/W
R/W
Accessibility
Initiators
External
Video Out
Audio In
R/W
R/—
R/W
Video In
R/—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/—
R/W
R/W
R/W
PCI
PRELIMINARY SPECIFICATION
Size of address range that will be locked into the instruction
cache
Sets ratios of external and internal clock frequencies
Powers up and down individual blocks
Status of video-in unit
Sets operation and interrupt modes for video in
Sets clock source (internal/external), frequency
Sets capture start x and y offsets
Sets capture size width and height
Capture modes: sets base address of Y-value array
Message/raw modes: sets base address of buffer 1
Capture modes: sets base address of U-value array
Message/raw modes: sets base address of buffer 2
Capture modes: sets base address of V-value array
Message/raw modes: sets size of buffers
Capture modes: address delta for adjacent U, V lines
Capture modes: address delta for adjacent Y lines
Status of video-out unit
Sets operation and interrupt modes for video out
Sets video-out clock frequency
Sets frame parameters (preset, start, length)
Sets field parameters (overlap, field-1 line, field-2 line)
Sets field parameters (starting pixel, frame width)
Sets image parameters (height, width)
Sets threshold for YTR interrupt, image v/h offsets
Sets overlay image parameters (start line/pixel, alpha)
Sets overlay image parameters (height, width)
Sets Y-component/buffer-1 starting address
Sets U-component/buffer-2 starting address
Sets V-component address/buffer-1 length
Sets overlay image address/buffer-2 length
Sets start-of-line-to-start-of-line address offsets (U, V)
Sets start-of-line-to-start-of-line addr. offsets (Y, overlay)
Sets operations for enhance video out
Sets YUV mask values foe the chroma-key process
Sets output clip values
Sets YUV chroma-key values
Sets delay cycles for genlock mode
Status of audio-in unit
Sets operation and interrupt modes for audio in
Sets clock ratios and internal/external clock generation
Sets format of serial data stream
Description
MMIO Register Summary
B-3
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