PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 187

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

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Philips Semiconductors
tion Both PLLs must be activated, i.e. {CD,CB,SD,SB}
must be equal to 0000 (binary value).
The operating limits of the internal PLLs are:
• 27 MHz < Output of the SDRAM PLL < 200 MHz
• 33 MHz < Output of the CPU PLL < 266 MHz
These are not the speed grades of the chips, just the PLL
limits.
CR (CPU-to-memory PLL ratio). The 3-bit CR field se-
lects one of five input-to-output clock ratios for the CPU
PLL. The input clock is the memory system clock; the
output clock determines the PNX1300 core operating fre-
quency. The default value is ‘0’, which implies a 1:1
CPU:memory ratio. See
SR (Memory-to-external PLL ratio). The 1-bit SR field
selects one of two memory-to-external clock ratios for
the memory interface PLL. The PLL input is PNX1300’s
external input clock TRI_CLKIN; the PLL output deter-
mines the operating frequency of the memory interface
and SDRAM devices. The default value is ‘0’, which im-
plies a 2:1 memory:external ratio. A value of ‘1’ implies a
3:1 ratio.
CD (CPU PLL disable). The 1-bit CD field determines
whether or not the CPU PLL is turned on. The reset value
is ‘1’, which disables operation of the CPU PLL and dis-
sipates almost no power. For normal operation the value
should be zero, enabling the CPU PLL.
CB (CPU PLL bypass). The 1-bit CB field determines
whether the input or the output of the CPU PLL drives
PNX1300’s core logic. The default value is ‘1’, which
causes the PNX1300 core to be clocked by the input of
the CPU PLL (i.e., the memory interface clock). A value
of ‘0’ causes normal operation, and the core is clocked by
the output of the CPU PLL.
Note that if both CB and SB are set to ‘1’ (bypass the
CPU PLL and the SDRAM PLL), PNX1300’s core logic is
effectively clocked at the external input frequency.
Note: it is illegal to use the output of a disabled PLL. For
example, it is illegal to have CD set to ‘1’ while CB is set
to ‘0’.
SD (SDRAM PLL disable). The 1-bit SD field deter-
mines whether or not the SDRAM PLL is turned on. The
default value is ‘1’, which disables the SDRAM PLL. In
this state, it dissipates almost no power. For normal op-
eration the value should be ‘0’, enabling the SDRAM
PLL.
SB (SDRAM PLL bypass). The 1-bit SB field deter-
mines whether the input or the output of the SDRAM PLL
drives the memory interface and memory devices. The
default value is ‘1’, which causes the memory system to
be clocked by the input of the SDRAM PLL (PNX1300’s
external input clock). A value of ’0’ causes normal oper-
ation, and the memory system is clocked by the output of
the SDRAM PLL.
Table 12-8
for other encoding.
12.7
The memory interface consists of 61 signal pins includ-
ing clocks (but excluding power and ground pins).
Table 12-9
Table 12-9. Memory Interface Signal Pins
12.8
The address mapping is determined by the state of the
rank-size bits and the bus width bit in the MM_CONFIG
register.
12.8.1
Table 12-10
PNX1300 data highway bus are mapped to main-memo-
ry address-bus and chip select pins (MM_A[13:0],
MM_CS#[3:0]) in 32-bit data bus mode.
Table 12-10. 32-bit Address Mapping
The column “Rank Addr./H.Way Bits” specifies which in-
ternal data-highway address bits select the preliminary
SDRAM rank. The actual rank used is subject to the lim-
itation implied by the relationship between SDRAM aper-
ture size (described in
PRELIMINARY SPECIFICATION
MM_CLK[1:0]
MM_CS#[3..0]
MM_RAS#
MM_CAS#
MM_WE#
MM_A[13:0]
MM_CKE[1:0]
MM_DQM[3:0]
MM_DQ[31:0]
16 MB
32 MB
Rank
4 MB
8 MB
Size
Name
MEMORY INTERFACE PIN LIST
ADDRESS MAPPING
H.Way
23–22
Addr.
25-24
Rank
24-23
Address Mapping in 32-bit mode
Bits
lists the interface signal pins.
–
shows how internal address bits from the
Memory bus clock
Chip selects for the four
memory ranks or Address
Row-address strobe
Column address strobe
Write enable
Address
Clock enable
Byte enables for dq bus
Bi-directional data bus
13-12
CS#3
CS#2
13-12
10–0
10–0
10–0
10–0
Pins
12,
Address
Row
Section
Function
H.Way
22–12
23–13
23–13
21–11
12-11,
12-11,
Bits
25,
24,
11,
SDRAM Memory System
13.2.1) and the rank size.
CS#3,
CS#2,
Pins
7–0
8–0
9–0
9–0
12,
12,
12
Address
Column
H.Way
10–6,
12–6,
12–6,
11–6,
Bits
4–2
4–2
4–2
4–2
25,
24,
11,
11,
11,
I/O
I/O
O
O
O
O
O
O
O
O
Pin
11
11
11
11
Address
Active...
Bank
High
High
High
High
High
Low
Low
Low
H.Way
Low
Bit
12-5
5