PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 153

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
• MMIO(AO_SERIAL) = 1 << 31; /* sets serial-master
• MMIO(AO_SERIAL) = (1 << 31) | (SCKDIV value); /*
Upon reset, transmission is disabled (TRANS_ENABLE
= 0), and buffer 1 is the active buffer (BUF1_ACTIVE=1).
The DSPCPU initiates transmission by providing two full
equal size buffers and putting their base address and
size in the BASE
buffers are assigned, transmission can be enabled by
writing a ‘1’ to TRANS_ENABLE. The AO hardware now
proceeds to empty buffer 1 by transmission of output
samples. Once buffer 1 empties, BUF1_EMPTY is as-
serted, and transmission continues without interruption
from buffer 2. If BUF1_INTEN is enabled, a SOURCE 12
interrupt request is generated.
Note that buffers must be 64-byte aligned (the six LSBs
of AO_BASE1, AO_BASE2 are zero). Buffer sizes must
be a multiple of 64 samples (the 6 LSB’s of AO_SIZE are
zero).
Table 9-11. AO MMIO DMA control fields
The DSPCPU is required to assign a new, full buffer to
BASE1 and perform an ACK1 before buffer 2 empties.
Transmission continues from buffer 2 until it is empty. At
that time, BUF2_EMPTY is asserted and transmission
LITTLE_ENDIAN
BASE1
BASE2
SIZE
TRANS_MODE
SIGN_CONVERT
mode, starts AO_SCK */
then set DIVIDER values */
Field Name
n
and SIZE registers. Once two valid
0 ⇒ big endian memory format (RESET
1 ⇒ little endian
Base Address of buffer1. Must be a 64-
byte aligned address in local SDRAM.
RESET default 0.
Base Address of buffer2. Must be a 64-
byte aligned address in local SDRAM.
RESET default 0.
DMA buffer size, in samples.
This number of mono samples or stereo
sample pairs is read from a DMA buffer
before switching to the other buffer.
Buffer size in bytes is as follows:
16 bps, mono : 2 * SIZE
32 bps, mono : 4 * SIZE
16 bps, stereo : 4 * SIZE
32 bps, stereo : 8 * SIZE
RESET default 0.
00 ⇒ mono, 32 bits/sample. (RESET
01 ⇒ stereo, 32 bits/sample
10 ⇒ mono, 16 bits/sample. Left data
11 ⇒ stereo, 16 bits/sample
Refer to
how TRANS_MODE and NR_CHAN
map to output behavior.
0 ⇒ leave MSB unchanged (RESET
default)
1 ⇒ invert MSB
(not applied to codec control fields)
default)
default). Left data and Right data
sent to each active output are the
same.
and Right data are the same.
Table 9-10
Description
for an explanation of
continues from the new buffer 1, etc. An ACK performs
two functions: it tells the AO unit that the corresponding
BASE register now points to a buffer filled with samples,
and it clears BUF_EMPTY. Upon receipt of an ACK, the
AO hardware removes the BUF_EMPTY related inter-
rupt request line assertion at the next DSPCPU clock
edge. Refer to the interrupt controller documentation for
details on interrupt handler programming. The AO inter-
rupt (SOURCE 12) should always be operated in level
sensitive mode
Table 9-12. AO DMA status fields (read only)
9.10
The AO unit has a private interrupt request line to the
DSPCPU vectored interrupt controller. It uses SRC# 12
(same as TM-1000/TM-1100/TM-1300 AO).
An interrupt is asserted as long as one or more of the
UNDERRUN, HBE, BUF1_EMPTY or BUF2_EMPTY
condition flags and the corresponding INTEN bit are as-
serted. Interrupts are sticky, i.e. an interrupt remains as-
serted until the software explicitly clears the condition
flag by an ACK_x action.
PRELIMINARY SPECIFICATION
BUF1_ACTIVE • If 1, buffer 1 will be used for the next sam-
BUF1_EMPTY
BUF2_EMPTY
HBE
UNDERRUN
Field Name
INTERRUPTS
• If 0, buffer 2 will contain the next sample
• If 1, buffer 1 is empty.
• If BUF1_INTEN is also 1, an interrupt
• BUF1_EMPTY is cleared by writing a ‘1’
• 0 after RESET.
• If 1, buffer 2 is empty.
• If BUF2_INTEN is also 1, an interrupt
• BUF2_EMPTY is cleared by writing a ‘1’
• 0 after RESET.
• Highway Bandwidth Error.
• 0 after RESET.
• Indicates that no data was transmitted
• An UNDERRUN error has occurred, i.e.
• If UDR_INTEN is also 1, an interrupt
• 0 after RESET.
ple to be transmitted.
(1 after RESET).
request (source 12) is asserted.
to ACK1, at which point the AO hardware
will assume that BASE1 and SIZE
describe a new full buffer.
request (source 12) is asserted.
to ACK2, at which point the AO hardware
will assume that BASE2 and SIZE
describe a new full buffer.
due to inability to read the local AO buffer
from SDRAM in time. This indicates an
insufficient allocation of PNX1300 High-
way bandwidth for the audio sampling
rate/mode.
the CPU failed to provide a full buffer in
time, and no samples were transmitted,
although requested by the D/A converter.
request (source 12) is pending. The
UNDERRUN flag can ONLY be cleared
by writing a ‘1’ to ACK_UDR.
Description
Audio Out
9-9