PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 177

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
ration words within the target device’s configuration
space.
FN (Function number). The FN field (bits 8..10 of
CONFIG_ADR) is used to specify one of up to eight func-
tions of the addressed PCI device.
DN (Device number). The DN field (bits 11..31 of
CONFIG_ADR) is used to select the targeted PCI de-
vice. Each bit corresponds to one of the 21 possible PCI
devices on a single PCI bus, i.e., each bit corresponds to
the idsel signal of one PCI device. Only one idsel sig-
nal—and, therefore, only one DN bit—can be asserted
during a given configuration cycle.
11.6.9
The 32-bit CONFIG_DATA register is used by the
DSPCPU to buffer data for a configuration cycle. When
PNX1300 is acting as the host CPU, it must configure the
PCI bus and devices. The DSPCPU writes or reads
CONFIG_DATA depending on whether it is performing a
write or read to a PCI device’s configuration space. See
Section 11.6.10, “CONFIG_CTL Register,”
formation on initiating configuration cycles.
11.6.10 CONFIG_CTL Register
The DSPCPU writes to CONFIG_CTL to trigger a config-
uration read or write cycle on the PCI bus. A PCI config-
uration read or write should not be performed during an
ongoing PCI I/O read or write.
The steps involved in a DSPCPU PCI configuration ac-
cess are:
1. Wait until BIU_STATUS io_cycle.Busy and
2. Write to CONFIG_ADR as described above, and (in
3. Write to CONFIG_CTL to start the read or write.This
4. Wait (polling or interrupt based) until
5. Retrieve the requested data in CONFIG_DATA (in
6. Clear config_cycle.Done by writing a ‘1’ to it.
Following are descriptions of the fields of CONFIG_CTL
and a discussion of how a DSPCPU write to
CONFIG_CTL triggers configuration cycles.
BE (Byte enables). The BE field (the four LSBs of
CONFIG_CTL) determines the state of PCIs 4-line c/be#
bus during the data phase of a configuration cycle. Since
the c/be# bus signals are active low, a ‘0’ in a BE field bit
means byte participates; a ‘1’ in a BE field bit means
‘byte does not participate.’
spondence between BE bits and bytes on the PCI bus
assuming little-endian byte order.
RW (Read/Write). The RW field (bit 4 of CONFIG_CTL)
determines whether the configuration cycle will be a read
or a write.
config_cycle.Busy are both de-asserted
case of a write operation) write to CONFIG_DATA.
action sets config_cycle.Busy.
config_cycle.Done is asserted by the hardware.
case of a read)
CONFIG_DATA Register
Table 11-16
shows the interpretation of RW.
Table 11-15
shows the corre-
for more in-
Table 11-15. BE field interpretation (assumes little-
endian byte ordering)
Table 11-16. RW Interpretation
A write by the DSPCPU to the CONFIG_CTL register
starts a configuration cycle on the PCI bus. The
CONFIG_DATA (for a write) and CONFIG_ADR regis-
ters must be set up before writing to CONFIG_CTL.
During a configuration read, the PCI interface drives the
PCI bus with the address from CONFIG_ADR and the
BE field from CONFIG_CTL. The returned data is buff-
ered in CONFIG_DATA. When the data is returned, the
PCI interface will generate a DSPCPU interrupt if the ap-
propriate IntE bit is set in BIU_CTL. Alternatively,
DSPCPU software can poll the appropriate “done” status
bin in BIU_STATUS. Finally, DSPCPU software reads
the CONFIG_DATA register in MMIO space to access
the data returned from the configuration cycle.
A write operation proceeds as for a read, except that PCI
data is driven from CONFIG_DATA during the transac-
tion and no data is returned in CONFIG_DATA.
11.6.11 IO_ADR Register
The 32-bit IO_ADR register is written by the DSPCPU to
set up for an access to a location in PCI I/O space. The
DSPCPU writes the address of the I/O register into
IO_ADR. See
more information on initiating I/O cycles.
11.6.12 IO_DATA Register
The 32-bit IO_DATA register is used by the DSPCPU to
set up for an access to a location in PCI I/O space. The
DSPCPU writes or reads IO_DATA depending on wheth-
er it is performing a write or read from IO space. See
Section 11.6.13, “IO_CTL Register,”
tion on initiating I/O cycles.
11.6.13 IO_CTL Register
The DSPCPU writes to IO_CTL to trigger a read or write
access to PCI I/O space. The function of this register is
similar to that of CONFIG_CTL, and the protocol for an I/
O cycle is similar to the configuration cycle protocol. A
PRELIMINARY SPECIFICATION
BE Bit
0
1
2
3
RW
0
1
0 ⇒ byte 0 (LSB) participates
1 ⇒ byte 0 (LSB) does not participate
0 ⇒ byte 1 participates
1 ⇒ byte 1 does not participate
0 ⇒ byte 2 participates
1 ⇒ byte 2 does not participate
0 ⇒ byte 3 (MSB) participates
1 ⇒ byte 3 (MSB) does not participate
Section 11.6.13, “IO_CTL Register,”
Interpretation
Interpretation
Write
Read
for more informa-
PCI Interface
11-13
for