PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 166

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
11.2
The following classes of operations invoked by PNX1300
cause the PCI interface to act as a PCI initiator:
• Transparent, single-word (or smaller) transactions
• Explicitly programmed single-word I/O or configura-
• Explicitly programmed multi-word DMA transactions.
• ICP DMA
11.2.1
From the point of view of programs executed by
PNX1300’s DSPCPU, there are three apertures into
PNX1300’s 4-GB memory address space:
• SDRAM space (0.5 to 64 MB; programmable)
• MMIO space (2 MB)
• PCI space
MMIO registers control the positions of the address-
space apertures (see
ture”). The SDRAM aperture begins at the address spec-
ified in the MMIO register DRAM_BASE and extends up-
ward to the address in the DRAM_LIMIT register. The 2-
MB
MMIO_BASE (defaults to 0xEFE00000 after power-up).
All addresses that fall outside these two apertures are
assumed to be part of the PCI address aperture. Refer-
ences by DSPCPU loads and stores to the PCI aperture
are reflected to external PCI devices by the coordinated
action of the data cache and PCI interface.
When a DSPCPU load or store targets the PCI aperture
(i.e., neither of the other two apertures), the DSPCPU’s
data cache automatically carries out a special sequence
of events. The data cache writes to the PCI_ADR and (if
the DSPCPU operation was a store) PCI_DATA regis-
ters in the PCI interface and asserts (load) or de-asserts
(store) the internal signal pci_read_operation (a direct
connection from the data cache to the PCI interface).
While the PCI interface executes the PCI bus transac-
tion, the DSPCPU is held in the stall state by the data
cache. When the PCI interface has completed the trans-
action, it asserts the internal signal pci_ready (a direct
connection from the PCI interface to the data cache).
When pci_ready is asserted, the data cache finishes the
original DSPCPU operation by reading data from the
PCI_DATA register (if the DSPCPU operation was a
load) and releasing the DSPCPU from the stall state.
Explicit Writes to PCI_ADR, PCI_DATA
The PCI_ADR and PCI_DATA registers are intended to
be used only by the data cache. Explicit writes are not al-
lowed and may cause undetermined results and/or data
corruption.
11-2
caused by DSPCPU loads and stores to the PCI
address aperture
tion read or write transactions
MMIO
PCI INTERFACE AS AN INITIATOR
DSPCPU Single-Word Loads/Stores
aperture
PRELIMINARY SPECIFICATION
Chapter 3, “DSPCPU Architec-
begins
at
the
address
in
11.2.2
Explicit programming by DSPCPU software is the only
way to perform transactions to PCI I/O space. DSPCPU
software writes three MMIO registers in the following se-
quence:
1. The IO_ADR register.
2. The IO_DATA register (if PCI operation is a write).
3. The IO_CTL register (controls direction of data move-
The PCI interface starts the PCI-bus I/O transaction
when software writes to IO_CTL. The interface can raise
a DSPCPU interrupt at the completion of the I/O transac-
tion (see BIU_CTL register definition in
“BIU_CTL
priate status bit (see BIU_STATUS register definition in
Section 11.6.4, “BIU_STATUS
I/O transactions should NOT be initiated if a PCI config-
uration transaction described below is pending. This is a
strict implementation limitation.
The fully detailed description of the steps needed can be
found in
11.2.3
As with I/O operations, explicit programming by
DSPCPU software is the only way to perform transac-
tions to PCI configuration space. DSPCPU software
writes three MMIO registers in the following sequence:
1. The CONFIG_ADR register.
2. The CONFIG_DATA register (if PCI operation is a
3. The CONFIG_CTL register (controls direction of data
The PCI interface starts the PCI-bus configuration trans-
action when software writes to CONFIG_CTL. As with
the I/O operations, the biu_status and BIU_CTL registers
monitor the status of the operation and control interrupt
signaling. Note that PCI configuration space transactions
should NOT be initiated if a PCI I/O transaction de-
scribed above is pending. This is a strict implementation
limitation.
The fully detailed description of the steps needed can be
found in
11.2.4
The PCI interface can operate as an autonomous DMA
engine, executing block-transfer operations at maximum
PCI bandwidth. As with I/O and configuration operations,
DSPCPU software explicitly programs DMA operations.
General-purpose DMA
For DMA between SDRAM and PCI, DSPCPU software
writes three MMIO registers in the following sequence:
1. The SRC_ADR and DEST_ADR registers.
2. The DMA_CTL register (controls direction of data
ment and which bytes participate).
write).
movement and which bytes participate).
movement and amount of data transferred).
Section 11.6.13, “IO_CTL Register.”
Section 11.6.10, “CONFIG_CTL Register.”
I/O Operations
Configuration Operations
DMA Operations
Register”) or the DSPCPU can poll the appro-
Philips Semiconductors
Register”). Note that PCI
Section 11.6.5,