PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 247

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

I
16.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 includes an
control many different multimedia devices such as:
• DMSDs - Digital multi-standard decoders
• DENCs - Digital encoders
• Digital cameras
• I
The key features of the
• Supports I
• I
• Support for the 7-bit addressing option of the I
• Provisions for full software use of I
Note that the I
parameters and/or code from a serial EEPROM as de-
scribed in
only active upon PNX1300 hardware reset and quiescent
afterwards.
A typical system using the
Figure
a series of slave devices through SCL and SDA. Note
that the bus has one pullup resistor for each of the clock
and data lines. The pullup should be set to a voltage no
higher than VREF_PERIPH.
Figure 16-1. Typical I
2
specification
for implementing software I
C Interface
2
2
C - Parallel I/O expanders
C data rate up to 400 kbits/sec
SCL
SDA
16-1. The PNX1300 is connected as a master to
I
2
C OVERVIEW
Section 13, “System
2
2
C single master mode
C pins are also used to load the initial boot
PNX1300
I
2
2
C
Slave
I
C system implementation
I
2
2
C
interface which can be used to
C
interface are:
I
2
Slave
C
I
2
2
C
C or similar protocols
interface is presented in
Boot”. The boot logic is
+ VREF_PERIPH
R
2
p
C interface pins
R
p
2
C
16.2
The following are the main
1000:
• The SEX bit is removed. Endian-ness is fixed.
• The
• The GDI bit now correctly indicates write-completion
• Clock stretching is always enabled.
16.3
The
shown in
Table 16-1. I
16.4
The
the programmer. The registers are mapped into the
MMIO address space and are fully accessible to the pro-
grammer.
sure compatibility with future devices, any undefined
MMIO bits should be ignored when read, and written as
‘0’s.
16.4.1
The IIC_AR is the I
master receive and transmit modes. This register is writ-
ten with the address(es) of the
bytecount for transmit/receive.
field definitions for the IIC_AR register.
Table 16-2. IIC_AR Register
PRELIMINARY SPECIFICATION
IIC_SDA
IIC_SCL
31:25
23:16
Signal
Bits
15:8
7:0
24
I
I
2
2
C
C
by Essam Abu-ghoush, Robert Nichols
I
COMPARED TO TM-1000
2
EXTERNAL INTERFACE
external interface is composed of two signals as
I
user interface consists of four registers visible to
2
C
Table
IIC_AR Register
C REGISTER SET
Figure 16-2
DIRECTION
Field Name
ADDRESS
clock rate is closer to 100/400 kHz
reserved
reserved
COUNT
2
Type
C External interface
I/O
O
16-1.
2
C
I
I
address register and is used in both
2
2
C serial data
C
shows the
7-bit slave device address.
Read/Write control bit
must be written to ‘0’
Byte count of requested transfer
Read as ‘0’
clock
Chapter 16
I
2
C
I
2
Table 16-2
Description
C
I
2
differences from TM-
C
Definition
slave device and the
register set. To en-
lists the bit-
16-1