PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 183

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

SDRAM Memory System
12.1
• Support of 256-Mbit SDRAMs organized in x16. The
• 16-bit memory interface support in addition to the 32-
12.2
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 connects to its local memory system with a
dedicated memory bus, shown in
interfaces only with SDRAM or SGRAM (synchronous
graphics DRAM with its DSF pin tied low); PNX1300 is
the only master on this bus.
A variety of device types, speeds, and rank
supported allowing a wide range of PNX1300 systems to
be built.
tures.The memory devices can have two or four banks.
The main memory interface provides all control and data
signals with sufficient drive capacity for a glueless con-
nection up to a 183-MHz memory system (for PNX1302,
166 MHz otherwise) with up to two memory devices. The
memory-system speed can be different from PNX1300
core speed; the ratio between the memory system clock
and PNX1300 core clock is programmable.
With current memory technology, PNX1300 supports a
glueless memory interface of up to 64MBytes with two
4×4M×16 SDRAM chips (two devices with 4 banks of
four million words, each 16 bits wide).
PNX1300 provides also a 16-bit memory interface (in-
stead of 32-bit only for TM-1300) for applications requir-
ing lower cost and lower performance. The available
bandwidth is then reduced by two and the latency on
cache misses is increased by two for the Instruction
1.
REFRESH counter must be changed. Refer to
Section 12.11
bit mode of TM-1300.
In this document, the term ‘rank’ is used to refer to a
group of memory devices that are accessed together.
Historically, the term ‘bank’ has been used in this con-
text; to avoid confusion, this document uses bank to re-
fer to on-chip organization (SDRAM devices have two
or four internal banks) and rank to refer to off-chip, sys-
tem-level organization.
NEW IN PNX1300/01/02/11
PNX1300 MAIN MEMORY OVERVIEW
Table 12-1
by Eino Jacobs, Chris Nelson, Thorwald Rabeler, Mohammed Yousuf, Luis Lucas
for more details.
summarizes the memory system fea-
Figure
12-1. This bus
1
sizes are
cache and by one SDRAM cycle for the Data cache on
critical word first demand.
The maximum amount of memory in the 16-bit mode is
32MBytes.
Table 12-1. Memory System Features
12.3
PNX1300’s local main memory is just one of three aper-
tures into the 4-GB address space of the DSPCPU:
• SDRAM (0.5 to 64 MB in size),
• MMIO (2 MB in size), and
• PCI (any address not in SDRAM or MMIO).
MMIO registers control the positions of the address-
space apertures. The SDRAM aperture begins at the ab-
solute
DRAM_BASE and extends upward to the address spec-
ified in the DRAM_LIMIT register. If the SDRAM aperture
overlaps the memory hole, the memory hole is ignored.
The MMIO aperture begins at the address in
MMIO_BASE, which defaults to 0xEFE00000 after pow-
er-up, and extends upwards 2 MB. (See
“DSPCPU Architecture,”
addresses that fall outside these two apertures are as-
sumed to be part of the PCI address aperture.
PRELIMINARY SPECIFICATION
Data width
Number of ranks
Memory size
Devices
supported
Clock rate
Bandwidth
Glueless interface • Up to 2 chips at 183 MHz (e.g., 32 MB
Signal levels
Characteristic
MAIN-MEMORY ADDRESS
APERTURE
address
16 and 32 bits
Four chip-select signals support up to four
ranks (can be used as addresses)
From 512 KB to 64 MB
• Jedec SGRAM (DSF tied low)
• Jedec SDRAM (×4, ×8, ×16, ×32)
• PC100/133 and later
Up to 183 MHz SDRAM speed (program-
mable ratio between
core clock and memory system clock)
732 MB/s (at 183 MHz and 32-bit i/f)
• Up to 4 chips at 166 MHz (e.g., 64 MB
3.3-V LVTTL
specified
memory with 4x1Mx32 SDRAM)
memory with 4x1Mx32 SDRAM)
for a detailed discussion.) All
Chapter 12
in
Comments
the
MMIO
Chapter 3,
register
12-1