TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 93

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

Address
3C
3D
7-0
Bit
7
6
5
4
3
2
1
RX ABORT
Reserved
Symbol
Counter
IPOLAL
RHIE
EOM
THIE
EHR
DJB
Receive Abort Counter: A 16-bit saturating counter that counts the num-
ber of abort sequences (1111111) that were detected. To read all 16 bits,
read this location to get the low byte and then read the common register
location (3EH) immediately after to get the high byte. The contents of this
counter should be disregarded when M13MODE = 1 or EHR = 0 or lead
M13X is high or floating. The counter is inhibited when DS3 loss of signal,
out of frame, AIS, or IDLE occurs. The counter is cleared when it is read by
the microprocessor. Single counts are not lost during a read cycle. When
this counter saturates, an interrupt request bit (IRABTS) is set in register
2BH.
DJB Control: When this bit is set to 0, the internal dejitter buffers (DJBs)
are bypassed and held in reset. The gapped receive DS1 clock and data
are output on the receive DS1 clock and data outputs (CR1-28 and DR1-
28). When this bit is set to a 1, the DJBs are taken out of reset and the
receive DS1 clock and data are passed through the DJBs before being out-
put on CR1-28 and DR1-28. Also if a local DS1 loopback is enabled via
registers 10H-13H and 1EH, while this bit is set to 1, the looped back DS1
data is dejittered.
Interrupt Polarity: The setting of this bit determines the polarity of the INT/
IRQ lead when that lead is driven active. When this bit is set to a 1, the
polarity of the INT/IRQ lead is active low. Otherwise, the polarity is active
high.
Receive Half Full Interrupt Enable: This bit controls the IRRHIS(2-0)
interrupt request bit logic to allow interrupts to occur for two different FIFO
fill conditions in the “010” state. A 1 enables the receive HDLC controller to
generate an interrupt when the receive PMDL FIFO is half full or more, or
has detected an end of message. When set to 0, the HDLC controller gen-
erates an interrupt when a receive PMDL FIFO full or overflow has
occurred, or at the end of the message.
Enable HDLC Receive Controller: A 1 enables the HDLC receive control-
ler. After flag detection and zero bit destuffing, the receive bytes from the
PMDL C-bits in the C-bit Parity format DS3 frame only are written into a
receive FIFO for a microprocessor read access via register 38H (receive
PMDL FIFO). A 0 disables the HDLC controller and disables the HDLC
receive interrupts.
Reserved: This bit is reserved and must always be written with a 0.
Transmit End Of Message: A 1 instructs the HDLC controller that the
transmit PMDL FIFO contains the last byte in the message. When the FIFO
has emptied, the FCS is calculated and transmitted and then this bit is
cleared.
Transmit Half Full Interrupt Enable: This bit controls the IRTHIS interrupt
request bit logic to allow interrupts to occur at the transmit PMDL FIFO
transition from more than half empty to half empty or message complete
only. A 1 enables the transmit HDLC controller to generate an interrupt
when the transmit PMDL FIFO transitions from more than half empty to half
empty or has detected an end of message. When set to 0, the HDLC con-
troller generates an interrupt only at the end of the message, or when a
FIFO underflow has occurred.
DATA SHEET
- 93 -
Description
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X