TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 32

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
Notes:
1. The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus
2. The SEL lead must be brought high for 2 transmit clock cycles before the start of a new read cycle.
ALE pulse width
ALE wait after RD
A/D(7-0) address setup time before ALE
A/D(7-0) address hold time after ALE
A/D(7-0) address hold time after RD
A/D(7-0) data output delay (to tri-state) after RD
A/D(7-0) data valid delay after RD
SEL wait after ALE
RD pulse width
RD wait after ALE
interface to operate. The RDY/DTACK output lead is always driven high when the SEL lead is low,
otherwise it is tri-stated, which corresponds to the behavior of the M13E device.
ALE
A/D(7-0)
SEL
RD
Figure 12. Microprocessor Read Cycle Timing - Multiplexed Interface
Parameter
t
PW(1)
t
SU
t
Address
OD(3)
DATA SHEET
t
H(1)
t
W(2)
- 32 -
Symbol
t
t
t
t
t
PW(1)
t
PW(2)
t
t
t
OD(1)
OD(2)
OD(3)
W(1)
t
W(2)
H(1)
H(2)
SU
t
H(2)
t
OD(2)
Min
180
95
20
30
25
10
25
t
PW(2)
Data
Typ
t
OD(1)
t
W(1)
212,000
Max
150
20
50
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns