TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 71

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

Address
02
03
Bit
7
6
5
4
3
2
1
0
7
M13MODE M13 Operating Mode: A 1 enables the M13X to operate in the M13 format
Symbol
LPTIME
Test Bit
INVCK
CBIT1
3LBK
IDLB
IDLA
1INV
DS1 Idle Code Selection: Three DS1 idle codes are provided, as shown in
the table below. The idle code selected via these control bits is common to
all DS1 channels selected for idle code transmission. One or more transmit-
ted DS1 channels is selected by writing a 1 in the corresponding IDLn bit(s)
in register locations 10H, 11H, 12H, and 13H, provided register location
1EH has not been set so as to select that DS1 channel for loopback.
Reserved for TranSwitch Testing Purposes: A 0 must be written into this
bit position.
DS3 Local Loopback: A 1 disables the DS3 receive input and causes the
DS3 transmit output to be looped back as receive data. Transmit data is
provided at the output (DS3DT). Please note that the DS3CR lead is still
monitored for a R3CKF alarm
Receive Loop Timing: A 1 disables the external transmit clock input
(XCK), and causes the DS3 receive clock to become the DS3 transmit
clock. If the DS3 receive clock fails in this mode, the M13X switches over to
the transmit clock (XCK). The demultiplexer becomes inoperative, but the
multiplexer and microprocessor interface continue to function.
Invert DS1 Transmit Clocks: A 1 causes all transmit DS1 data inputs
(DTn) to be sampled on the falling edges of their respective DS1 clock
inputs (CTn). This is provided for back-to-back M13X operation.
Invert DS1 Transmit Data: A 1 causes the transmit data inputs for all DS1
channels (DTn) to be inverted within the M13X.
mode. Using ANSI T1.107-1995 terminology, the M13X performs M12
mode and M23 mode muxing and demuxing where the DS2 and DS3 C-
bits are used for stuffing/destuffing. A 0 enables the M13X to operate in the
C-bit parity mode as specified in the ANSI T1.107-1995.
C-bit Number 1 State: This bit is updated each frame with the state of the
received C1 bit. The C1 bit is used to identify the DS3 application according
to the table shown below:
In addition, any C-bit that is received as 0 will increment the C-bit Equal to
Zero Counter in register 22H.
IDLB
X
0
1
IDLA
0
0
1
DATA SHEET
C1 Value
Random
All 1s
- 71 -
Quasi-Random Signal (2
suppression.
Framed Extended Super Frame (ESF) signal format
which consists of an S-bit pattern of 001011 in every
fourth signaling bit position, CRC-6 pattern, and ones
in the 64 kbit/s channels 1 through 24.
Unframed all ones signal (AIS).
Description
DS1 Idle Code Selected
Application
M13 format
C-bit parity format
20
- 1 QRS) including zero
Ed. 4, September 2000
TXC-03305
TXC-03305-MB
M13X