TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 55

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

M13X
DATA SHEET
TXC-03305
practice is not recommended since it complicates the process, requires additional resources and takes extra
effort to ensure that the receive PMDL FIFO does not overflow.
If the end user desires to receive a message longer than what could be stored in the receive FIFO, the follow-
ing procedure can be used: First configure the receiver to generate an interrupt at the end of message or if the
receive PMDL FIFO becomes full or overflows by writing a 0 to control bit RHIE (bit 5) in register 3DH and writ-
ing mask bits MIRRHIS(2-0) (bits 7 - 5 in register 35H) to 110 and MIRRXFS1,0 (bits 4 and 3) in register 35H
to 11. Initialize the receive FIFO by reading the RX PMDL FIFO register in register 38H repeatedly until the
FIFO is emptied, which is indicated by RX PMDL FIFO DEPTH = 00H in register 3AH. Then enable the
receiver by writing a 1 to control bit EHR (bit 4) in register 3DH.
The receiver will generate an interrupt when the receive PMDL FIFO is full or has overflowed or a message has
been received. The end of a normal, valid received message is indicated by IRRHIS(2-0) equal to 010 and
IRRXFS(1-0) not equal to 10 or 11. When an interrupt occurs, the end user will read the RX PMDL FIFO
DEPTH register and then the IRRXFS(1-0) and the IRRHIS(2-0) bits. If the IRRHIS(2-0) and IRRXFS(1-0) bits
indicate that the end of the message has occurred and receive PMDL FIFO full or overflow has not occurred,
then the number of bytes indicated by the RX PMDL FIFO DEPTH register is read out of the receive PMDL
FIFO since a complete message has been received. If the IRRHIS(2-0) bits do not indicate the end of a mes-
sage, the IRRHIS(2-0) bits are checked to see the status of the receive PMDL FIFO. If the receive PMDL FIFO
is half full, then the end user reads out the message segment indicated by the RX PMDL FIFO DEPTH register
and stores it. This process is repeated until the IRRHIS(2-0) bits indicate that the end of a message has been
received. If an interrupt occurs while reading a message segment from the receive PMDL FIFO, the process
above should be repeated.
In the event that the receive PMDL FIFO overflows, the receive PMDL data will be lost. The receive PMDL
FIFO must be cleared out. An FCS error will not necessarily result due to the loss of the data. This is because
the FCS is checked before the PMDL data is written into the receive PMDL FIFO. In this case, when the
IRRXFS(1-0) bits indicate that the receive PMDL FIFO has overflowed, the RX PMDL FIFO DEPTH register,
and perhaps previous values of the RX PMDL MESSAGE LENGTH register (if the receive PMDL FIFO was not
empty before the current frame was written to the receive PMDL FIFO) should be used to calculate how much
of the data in the receive PMDL FIFO belongs to the corrupted frame. This will allow the end user’s software to
manage the data in the receive PMDL FIFO and know which data belongs to a good frame and which belongs
to a corrupted frame.
COUNTERS
There are up to eight 8-bit or 16-bit performance counters available in the M13X device depending on the set-
ting of the M13X lead. The table below describes counter availability. The address shown in the table is that of
the low byte for 16-bit counters.
All counters clear when read. All 8-bit counters saturate at a count of FFH. All 16-bit counters saturate at a
count of FFFFH and have an associated interrupt request bit to indicate when the counter has saturated. Two
read cycles are needed to read a 16-bit counter. A Common Register is provided at address 3EH for storing the
high (most significant) byte of a 16-bit counter when its low byte is read. That is, when the low (least significant)
byte of a 16-bit counter is read, the high byte of that counter is simultaneously written to the Common Register
and can subsequently be read from that register provided that another 16-bit counter read is not performed
first. The high byte of a 16-bit counter is not directly accessible via the microprocessor interface; address 3EH
must be used to read its contents.
TXC-03305-MB
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Ed. 4, September 2000