TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 70

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
Address
(cont.)
00
01
Bit
2
1
0
7
6
5
4
3
2
1
0
Symbol
T3CKF
Test Bit
Test Bit
CBITE
PBITE
T3AIS
T3IDL
FEBE
XR2
XR1
XT
Transmit DS3 Clock Failure: A transmit DS3 clock failure alarm occurs,
and this bit is set to 1, when the transmit input clock (XCK) is stuck high or
low for 6-7 DS3CR clock cycles. A failure causes the receive clock to
become the transmit clock. This permits the M13X microprocessor interface,
multiplexer, and DJB logic to function. Recovery to 0 occurs when the XCK
clock returns for one cycle.
Receive DS3 X-bit Number 2: This bit position indicates the receive state
of X2. This bit position is updated each frame.
Receive DS3 X-bit Number 1: This bit position indicates the receive state
of X1. This bit position is updated each frame.
Reserved for TranSwitch Testing Purposes: A 0 must be written into this
bit position.
Reserved for TranSwitch Testing Purposes: A 0 must be written into this
bit position.
Transmit DS3 Alarm Indication Signal: A 1 causes the M13X to transmit
a DS3 AIS. The type of AIS sent is determined by the states written into bit
1 (T3AIS1) and bit 0 (T3AIS0) in register 21H.
Transmit DS3 Idle Signal: To transmit a DS3 idle signal, (i) a 1 must be
written in this bit 4 (T3IDL) register location, and (ii) a 1 must also be written
(if not already written) into bit 0 (XT) of this register 01H, and (iii) bit 0
(T3AIS0) and bit 1 (T3AIS1) of register 21H must also be set to 0.
Transmit Far End Block Error: A 1 causes the M13X to transmit a single
FEBE error indication (C10, C11, and C12 equal to 0) in the next DS3
frame. This bit is not self-clearing; to send an additional FEBE indication,
the microprocessor must first write this bit with a 0 and then with a 1.
Transmit P-Bit Parity Error: A 1 causes the M13X to transmit a single P-
bit parity error in the next DS3 frame. The P-bit error is transmitted by
inverting the value of the two calculated bits. This bit is not self-clearing; to
send an additional error, the microprocessor must first write this bit with a 0
and then with a 1.
Transmit C-Bit Parity Error: A 1 causes the M13X to transmit a single C-
bit parity error in the next available DS3 frame when the M13X is operating
in the C-bit parity mode. The C-bit error is transmitted by inverting the calcu-
lated C-bit parity bits in subframe 3 (C7, C8, and C9). This bit is not self-
clearing; to send an additional error, the microprocessor must first write this
bit with a 0 and then with a 1.
Transmit X-Bits: The X-bits may be used to transmit a yellow alarm or may
be used as a low speed signaling channel. A 1 or 0 causes the M13X to
transmit a 1 or 0 for both X1 and X2.
Note:
T3IDL, bit 4 in this register 01H).
This bit must be set to 1 when transmitting DS3 idle signal (see
DATA SHEET
- 70 -
Description