TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 5

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

M13X
DATA SHEET
TXC-03305
BLOCK DIAGRAM DESCRIPTION
Figure 1 shows a simplified block diagram of the M13X and its signal leads. The M13X is packaged in a 208-
lead small outline Plastic Ball Grid Array (PBGA) package or a 208-lead Plastic Quad Flat Package (PQFP).
The PQFP version is intended to be used as a replacement for TranSwitch’s M13E device (TXC-03303-AIPQ)
and is not recommended for new designs. The PBGA version is intended for new designs.
The M13X in the PBGA or PQFP packages, with the exception of the boundary scan, can be configured to be
functionally compatible with, and have the same memory map as, the M13E device, by applying a high to the
M13X lead. The enhanced features included in the M13X can be enabled by applying a low to the M13X lead.
These enhanced M13X features are:
• Transmit/receiv e PMDL (Path Maintenance Data Link) controller
• Interrupt request lead with programmable polarity and associated interrupt mask bits
• Integrated dejitter buffer (DJB) on all receive DS1 outputs with optional bypass capability
• 16-bit performance counters.
• NEW bit in register 1DH does not become set to one again after it is cleared when a constant FEAC message is
received.
When the M13X lead is set to high, the M13X enhanced features listed above are disabled and cannot be
accessed.
In the receive direction, DS3 data (DS3DR) is clocked into the M13X on rising edges of the DS3 input clock
(DS3CR). The data and clock signals may be derived from any line interface unit such as TranSwitch’s ART,
ARTE, DART or DS3LIM-SN, or from other line circuitry.
The DS3 Frame Sync block searches for and locks to the DS3 frame, as specified in Bellcore GR-499-CORE
“Transport System Generic Requirements,” and in ANSI T1.107-1995. The M13X receiver monitors the DS3
signal for out of frame, loss of signal, a DS3 AIS, DS3 idle signal, P-bit parity, the state of the X-bits, and loss of
clock. The DS3 AIS detection mechanism is software selectable, with a choice of six detectors. These range
from full compliance to T1.107-1995 to unframed all ones AIS detection. Control bits are also provided in mem-
ory which allow all, some of, or none of the DS3 alarms to cause the insertion of AIS into the receive DS1
channels.
In the M13 format mode, destuffing from DS3 to DS2 is performed based on the states of the C-bits in the DS3
subframes. If two or three of the C-bits in a subframe are ones, the associated stuff bit is interpreted as being a
stuff bit and is removed from the data stream and discarded.
In the C-bit parity mode, the C-bits are allocated for network performance. The M13X performs Far End Alarm
and Control (FEAC) detection, C-bit parity error detection, and Far End Block Error (FEBE) detection. FEAC
loopback requests and alarm/status information are provided in the memory map. In addition, the states of 14
C-bits (C2, C3, C4, C5, C6, C13, C14, C15, C16, C17, C18, C19, C20, and C21) are provided at a serial inter-
face (CDR), along with an output clock signal (CCKR), framing pulse (CFMR), and data link indicator pulse
(CDCCR). The data link indicator pulse identifies the location of the data link bits, C13, C14, and C15. If the
M13X lead is tied low, the receive PMDL (Path Maintenance Data Link) controller can be enabled via a control
bit. The receive PMDL controller is used to extract PMDL messages of any length. FCS error detection,
ABORT detection, End of Message, Start of Message, Invalid Frame Detected, and receive PMDL FIFO status
can be monitored via the microprocessor interface.
The M13X synchronizes and extracts the 28 DS1 channels from the seven DS2 channels. Each of the DS2
channels is monitored for out of frame. The M13X may generate AIS in each of the DS1 signal tributaries cor-
responding to the DS2 channel(s) that lost frame, depending on the DS1 AIS alarm insertion control bits. DS2
to DS1 destuffing is based on the states of the three C-bits in each DS2 subframe. If two or three of the C-bits
in one of the DS2 subframes are ones, the stuff bit for that subframe is discarded. In the M13 format mode, the
DS2 C-bits or stuffing bits are used for DS1 remote loopback requests for either the M13 or C-bit Parity format
TXC-03305-MB
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Ed. 4, September 2000