TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 48

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
JITTER GENERATION
In the absence of input jitter on any clock applied to the M13X device, the jitter generated at the RX DS1 output
(with the DJB function enabled) shall be less than 0.3 UIrms and also less than 1.0 UIpp over the jitter frequen-
cies of 10 Hz - 40 KHz ([GR-499] R7-7 section 7.3.3 and Table 7-1) and over all of the DS1 and DS3 clock off-
sets. This requirement applies only to a multiplexer demultiplexer pair.
Jitter generation criteria for the DS3 interface is not defined at this time. As a goal, the jitter at the TX DS3 out-
put of a ARTE/M13X pair is required to be less than 5 UIpp over a jitter frequency range of 10Hz - 400 KHz and
0.1 UIpp over a jitter frequency range of 30 KHz - 400 KHz.
JITTER ENHANCEMENT
The DS1 jitter output at an RX DS1 of the M13X is less than 5.0 UIpp over a jitter frequency range of 10 KHz -
40 KHz, after that DS1 signal went through 12 (or more) M13X multiplexer/demultiplexer pairs. This require-
ment is met when the 1st DS1 signal has 4.0 UI applied to it over a jitter frequency range of 10 Hz - 350 Hz.
This requirement does not need to be met when the DJBs are bypassed but must be met when they are
enabled. Also, no bit errors occur.
RESIDUAL JITTER
When the DJBs are enabled and the demultiplexed DS1 signals do not have any jitter on them, the DS1 jitter
output of the M13X is about 0.30 UIpp and 0.038 UIrms over a 10Hz - 40 KHz jitter frequency range and about
0.028 UIpp and 0.014 UIrms over an 8 KHz - 40 KHz jitter frequency range for all DS1 and DS3 clock offset fre-
quencies.
DATA SHEET
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