TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 34

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

TXC-03305-MB
Ed. 4, September 2000
M13X
TXC-03305
Notes:
1. The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus
2. The SEL lead must be brought high for 2 transmit clock cycles before the start of a new read cycle.
A(7-0) address hold time after RD
A(7-0) address setup time before SEL
D(7-0) data valid delay after RD
D(7-0) data float time after RD
RD pulse width
SEL setup time before RD
SEL hold time after RD
interface to operate. The RDY/DTACK output lead is always driven high when the SEL lead is low,
otherwise it is tri-stated, which corresponds to the behavior of the M13E device.
A(7-0)
D(7-0)
SEL
RD
Parameter
Figure 14. Microprocessor Read Cycle Timing - Intel Interface
t
SU(1)
t
SU(2)
DATA SHEET
Symbol
t
t
t
SU(1)
SU(2)
t
t
H(1)
H(2)
PW
t
t
D
F
- 34 -
t
Min
D
0.0
0.0
20
80
10
t
PW
Typ
t
H(1)
212,000
t
H(2)
Max
t
60
80
F
Unit
ns
ns
ns
ns
ns
ns
ns