TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet - Page 51

• Manufacturer Part Number: TXC-03305AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03305AIPQ

• Lead Free Status / RoHS Status: Not Compliant

ANSI T1.107 LAPD messages to be received. Interrupts and status information are provided to facilitate FIFO
servicing by the microprocessor.
The HDLC receiver is enabled when a 1 is written to control bit EHR (bit 4) in register 3DH. When enabled, the
receive PMDL C-bits (C13, C14, and C15) are extracted from the receive DS3 stream. The flag sequence is
checked to determine the byte boundary. After the octet boundary is established, the first non-flag octet signi-
fies the start of the information field. At this point, the HDLC receiver will remove the stuffed 0 bits and place
the message contents, aligned to octet boundaries, into the 159-byte receive PMDL FIFO. It is important to
note that the first bit received is the least significant bit and goes into bit location 0
controller will check the FCS to ensure that it is correct. The received FCS is not stored in the FIFO and is dis-
carded after being checked. Only the de-stuffed information between the opening and closing flags is written to
the receive PMDL FIFO. Please note that receive PMDL FIFO overflow does not necessarily result in an FCS
error since the FCS is checked before data is written into the receive PMDL FIFO. If the FCS check fails, then
the RX FCS ERROR Counter at address 3BH increments and the IRRHIS(2-0) bits in register 2CH are set to
011 to signal that an FCS error has occurred. The RX FCS ERROR Counter is a read-only 16-bit counter that
clears on read. FCS Error Counts are not lost during a read. If an abort sequence is detected (i.e., an octet that
contains more than 6 consecutive 1s is detected), only the information field received up to that point is written
to the receive PMDL FIFO. Furthermore, the RX ABORT Counter at register 3CH increments, and the
IRRHIS(2-0) bits in register 2CH are set to 100 to signal that an abort has occurred. The RX ABORT Counter
is a 16-bit read only counter that clears on read. ABORT counts are not lost during a read of this counter. The
RX PMDL FIFO DEPTH and RX PMDL MESSAGE LENGTH registers, at 3AH and 39H, are also updated
accordingly, as described in the paragraphs below. The receive DS3 C-bit interface operation is not affected by
the setting of the EHR control bit. When EHR = 0, the receive PMDL controller is disabled, and no interrupt
requests are generated.
The receive PMDL FIFO is monitored for fill level, with maskable interrupts provided. Bits IRRXFS1 and
IRRXFS0 (bits 4 and 3) in register 2CH indicate when the receive PMDL FIFO is equal to or greater than half
full, full, and overflowed. An interrupt may also be activated at the end of the message, or when the FIFO is half
full, using the RHIE control bit (bit 5) in register 3DH to control the conditions for which interrupt request bits
IRRHIS(2-0) (bits 7 - 5) in register 2CH change. If it is desired to signal an interrupt at the end of a message,
the RHIE control bit can be set to 0. Then the HDLC controller will generate an interrupt only on the completion
of the message. If mask bits MIRRHIS(2-0) (bits 7 - 5 in register 35H) are set to 110, an interrupt will occur
when IRRHIS(2-0) = X1X or 1XX; IRRHIS(2-0) will also hold the latched value. The controller will generate an
interrupt when the FIFO is half filled by setting RHIE
now the interrupt based on IRRHIS(2-0) = 010 will occur both at the end of message and when the FIFO
reaches half full. This same function may be accomplished by leaving RHIE = 0 and by monitoring the FIFO fill
level using status bits IRRXFS1 and IRRXFS0 to detect FIFO fullness. To generate an interrupt from the
IRRXFS1 and IRRXFS0 interrupt request bits, mask bits MIRRXFS1 and MIRRXFS0 (bits 4 and 3) in register
35H should be set to 11; when the receive PMDL FIFO is equal to or more than half full, interrupt request bits
IRRXFS1 and IRRXFS0 (bits 4 and 3) in register 2CH will be set to 01 and an interrupt will be generated.
The RX PMDL FIFO DEPTH register at address 3AH provides the number of bytes presently stored in the
receive FIFO. Bits IRRHIS(2-0) (bits 7-5 in register 2CH) provide message status and error indications. The
receive PMDL controller will generate a maskable interrupt for start of message detected, valid message
received, FCS in error, message aborted, and invalid frame received. The message bytes are read by the
microprocessor from the RX PMDL FIFO at register 38H. Bit 0 corresponds to the first bit received in a byte.
To accommodate back-to-back messages, a RX PMDL MESSAGE LENGTH register is provided at address
39H, which is loaded with the length of the received message, in bytes, at the end of every message (valid
1. TranSwitch bit numbering format is used here. Bits are ordered 7-0 (most significant bit - least significant bit).
2. CAUTION: The first bit transmitted/received in the HDLC protocol is the least significant bit. See sections 2.8.1
3. This setting of RHIE is used when the message is expected to be longer than 159 bytes.
and 2.8.2 in [Q.921]. Please also note that in [Q.921] bits are numbered 8-1 (most significant bit-least significant
bit) instead of 1-8 (most significant bit-least significant bit) as in some other documents.
DATA SHEET
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3
= 1; mask bits MIRRHIS(2-0) should be set to 110, but
1
of the octet.
Ed. 4, September 2000
TXC-03305
2
TXC-03305-MB
The HDLC
M13X