ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 60

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC836
BAUD RATE GENERATION USING TIMER 3
The high integer dividers in a UART block means that high
speed baud rates are not always possible using some particular
crystals, e.g., using a 12 MHz crystal, a baud rate of 115200 is
not possible. To address this problem, the ADuC836 has added
a dedicated baud rate timer (Timer 3) specifically for generating
highly accurate baud rates.
Timer 3 can be used instead of Timer 1 or Timer 2 for generating
very accurate high speed UART baud rates including 115200 and
230400. Timer 3 also allows a much wider range of baud rates to
be obtained. In fact, every desired bit rate from 12 bits to 393216
bits can be generated to within an error of ±0.8%. Timer 3 also
frees up the other three timers allowing them to be used for dif-
ferent applications. A block diagram of Timer 3 is shown in
Figure 57.
Two SFRs (T3CON and T3FD) are used to control Timer 3.
T3CON is the baud rate control SFR, allowing Timer 3 to be
used to set up the UART baud rate, and setting up the binary
divider (DIV).
Bit
7
6
5
4
3
2
1
0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION)
FRACTIONAL
DIVIDER
Name
T3EN
–––
–––
–––
–––
DIV2
DIV1
DIV0
CORE
CLK*
Table XXXIII. T3CON SFR Bit Designations
Figure 57. Timer 3, UART Baud Rates
(1 + T3FD/64)
Description
Set to enable Timer 3 to generate the baud rate.
When set PCON.7, T2CON.4 and T2CON.5
are ignored. Cleared to let the baud rate be
generated as per a standard 8052.
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
Binary Divider Factor
DIV2 DIV1 DIV0 Bin Divider
0
0
0
0
1
1
1
1
2
16
DIV
2
0
0
1
1
0
0
1
1
T3 RX/TX
CLOCK
RX CLOCK (FIG 44)
TIMER 1/TIMER 2
0
1
0
1
0
1
0
1
1
1
TX CLOCK (FIG 44)
0
0
TIMER 1/TIMER 2
1
2
4
8
16
32
64
128
T3EN
TX CLOCK
RX
CLOCK
–60–
The appropriate value to write to the DIV2-1-0 bits can be cal-
culated using the following formula where f
the PLL, as described in the On-Chip PLL section. Note that the
DIV value must be rounded down.
T3FD is the fractional divider ratio required to achieve the
required baud rate. We can calculate the appropriate value for
T3FD using the following formula. Note that the T3FD should
be rounded to the nearest integer.
Once the values for DIV and T3FD are calculated, the actual
baud rate can be calculated using the following formula:
For a baud rate of 115200 while operating from the maximum
core frequency (CD = 0), we have:
Therefore, the actual baud rate is 115439 bits.
Ideal
Baud
230400
115200
115200
57600
57600
57600
38400
38400
38400
38400
19200
19200
19200
19200
19200
9600
9600
9600
9600
9600
9600
38400
T FD
Table XXXIV. Commonly Used Baud Rates Using Timer 3
3
DIV
=
(
=
2 12 582912
Actual Baud Rate
log
×
CD
0
0
1
0
1
2
0
1
2
3
0
1
2
3
4
0
1
2
3
4
5
0
(
T FD
12582912 32 115200
.
3
DIV
=
=
DIV
0
1
0
2
1
0
3
2
1
0
4
3
2
1
0
5
4
3
2
1
0
3
log
2
)
DIV
/
(



2
2
32
1
=
×
×
×
×
2
Baud Rate
log
×
T3CON
80H
81H
80H
82H
81H
80H
83H
82H
81H
80H
84H
83H
82H
81H
80H
85H
84H
83H
82H
81H
80H
83H
f
115200
DIV
CORE
f
Baud Rate
CORE
( )
2
2
×
×
(
T FD
)
)
f
/ log
3
CORE
CORE
−
−
64



64
T3FD
2DH
2DH
2DH
2DH
2DH
2DH
12H
12H
12H
12H
12H
12H
12H
12H
12H
12H
12H
12H
12H
12H
12H
12H
2 1 77 1
is the output of
+
=
=
64
45 22 2
.
)
.
=
%
Error
0.2
0.2
0.2
0.2
0.2
0.2
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
REV. A
=
Dh