ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 44

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
7
6
5
4
3
2
1
0
*The CPOL and CPHA bits should both contain the same values for master and slave devices.
SERIAL PERIPHERAL INTERFACE
The ADuC836 integrates a complete hardware Serial Peripheral
Interface (SPI) interface on-chip. SPI is an industry-standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously, i.e., full-
duplex. It should be noted that the SPI pins SCLOCK and MOSI
are multiplexed with the I
are controlled via the I2CCON SFR only if SPE is clear. SPI can
be configured for master or slave operation and typically consists of
four pins:
SCLOCK (Serial Clock I/O Pin), Pin 26
The master clock (SCLOCK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. A single data bit is transmitted and received in each
SCLOCK period. Therefore, a byte is transmitted/received after
eight SCLOCK periods. The SCLOCK pin is configured as an
output in master mode and as an input in Slave mode. In Master
mode, the bit rate, polarity, and phase of the clock are controlled
by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR
(see Table XXI). In Slave mode, the SPICON register will have
to be configured with the phase and polarity (CPHA and CPOL)
as the master, as for both Master and Slave modes the data is
transmitted on one edge of the SCLOCK signal and sampled on
the other.
ADuC836
Name
ISPI
WCOL
SPE
SPIM
CPOL*
CPHA*
SPR1
SPR0
Description
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
Write Collision Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to enable the I
SPI Master/Slave Mode Select Bit.
Set by user to enable Master mode operation (SCLOCK is an output).
Cleared by user to enable Slave mode operation (SCLOCK is an input).
Clock Polarity Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
SPI Bit Rate Select Bits.
These bits select the SCLOCK rate (bitrate) in Master mode as follows:
SPR1
0
0
1
1
In SPI Slave mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin 13), can be read via the SPR0 bit.
2
C pins SCLOCK and SDATA.The pins
SPR0
0
1
0
1
Table XXI. SPICON SFR Bit Designations
Selected Bit Rate
f
f
f
f
CORE
CORE
CORE
CORE
/2
/4
/8
/16
2
C interface.
–44–
MISO (Master In, Slave Out Data I/O Pin), Pin 14
The MISO (master in slave out) pin is configured as an input line
in Master mode and an output line in Slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as byte-
wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin), Pin 27
The MOSI (master out slave in) pin is configured as an output
line in Master mode and an input line in Slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte-
wide (8-bit) serial data, MSB first.
SS (Slave Select Input Pin), Pin 13
The Slave Select (SS) input pin is only used when the ADuC836
is configured in SPI Slave mode. This line is active low. Data is
only received or transmitted in Slave mode when the SS pin is low,
allowing the ADuC836 to be used in single master, multislave SPI
configurations. If CPHA = 1, the SS input may be permanently
pulled low.With CPHA = 0, the SS input must be driven low
before the first bit in a byte wide transmission or reception and
return high again after the last bit in that byte-wide transmission or
reception. In SPI Slave mode, the logic level on the external SS pin
(Pin 13) can be read via the SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
REV. A