ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 23

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION
Overview
The ADuC836 incorporates two independent - ADCs (primary
and auxiliary) with on-chip digital filtering intended for the mea-
surement of wide dynamic range, low frequency signals such as
those in weigh-scale, strain gage, pressure transducer, or tempera-
ture measurement applications.
Primary ADC
This ADC is intended to convert the primary sensor input. The
input is buffered and can be programmed for one of eight input
ranges from ±20 mV to ±2.56 V being driven from one of three
differential input channel options AIN1/2, AIN3/4, or AIN3/2.
The input channel is internally buffered, allowing the part to
handle significant source impedances on the analog input and
REV. A
USER TO EASILY DETECT
CURRENTS ALLOW THE
BURNED OUT OR GONE
IF A TRANSDUCER HAS
TWO 100nA BURNOUT
BURNOUT CURRENTS
OPEN-CIRCUIT.
FULLY DIFFERENTIAL PAIR OPTIONS AND
ADDITIONAL INTERNAL SHORT OPTION
(AIN2–AIN2). THE MULTIPLEXER IS
CONTROLLED VIA THE CHANNEL
A DIFFERENTIAL MULTIPLEXER
ALLOWS SELECTION OF THREE
SELECTION BITS IN ADC0CON.
ANALOG MULTIPLEXER
AIN1
AIN2
AIN3
AIN4
ANALOG INPUT CHOPPING
ALTERNATELY REVERSED
EXCELLENT ADC OFFSET
CONVERSION CYCLE.
AND OFFSET DRIFT
CHOPPING YIELDS
THE INPUTS ARE
PERFORMANCE.
MUX
THROUGH THE
AGND
AV
DD
CHOP
FOR THE ANALOG INPUTS,
IMPEDANCE INPUT STAGE
ALLOWING SIGNIFICANT
THE BUFFER AMPLIFIER
BUFFER AMPLIFIER
EXTERNAL SOURCE
GAIN AMPLIFIER ALLOWS
PRESENTS A HIGH
RANGES FROM 20mV TO
2.56V (EXT V
PROGRAMMABLE GAIN
THE PROGRAMMABLE
EIGHT UNIPOLAR AND
EIGHT BIPOLAR INPUT
IMPEDANCES.
BUFFER
AMPLIFIER
Figure 7. Primary ADC Block Diagram
REF
PGA
REFIN(–) REFIN(+)
= 2.5V).
OF WHICH IS ALSO CHOPPED)
CIRCUITRY TESTS FOR OPEN OR
DATA STREAM (THE OUTPUT
REPRESENTS THE SAMPLED
THE MODULATOR PROVIDES
THE DUTY CYCLE OF WHICH
SHORTED REFERENCE INPUTS.
SELECTED VIA THE XREF0 BIT
ANALOG INPUT VOLTAGE.
OPERATION. THE EXTERNAL
A HIGH FREQUENCY 1-BIT
THE EXTERNAL REFERENCE
TO THE DIGITAL FILTER,
FACILITATES RATIOMETRIC
INPUT TO THE ADuC836 IS
REFERENCE VOLTAGE IS
MODULATOR
REFERENCE DETECT
- MODULATOR
–23–
DIFFERENTIAL AND
DIFFERENTIAL
-
IN ADC0CON.
REFERENCE
allowing R/C filtering (for noise rejection or RFI reduction) to be
placed on the analog inputs if required. On-chip burnout currents
can also be turned on. These currents can be used to check that
a transducer on the selected channel is still operational before
attempting to take measurements.
The ADC employs a - conversion technique to realize up to
16 bits of no missing codes performance.The - modulator
converts the sampled input signal into a digital pulse train whose
duty cycle contains the digital information. A Sinc
low-pass filter is then employed to decimate the modulator output
data stream to give a valid data conversion result at programmable
output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A
chopping scheme is also employed to minimize ADC offset errors.
A block diagram of the primary ADC is shown in Figure 7.
- ADC
PROGRAMMABLE
DIGITAL
FILTER
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
THE - ARCHITECTURE
RATE AND BANDWIDTH OF THIS
CHOPPED TO REMOVE
FILTER ARE PROGRAMMABLE
ENSURES 24 BITS NO
MISSING CODES. THE
THE SINC 3 FILTER REMOVES
ENTIRE - ADC IS
DRIFT ERROR.
PROGRAMMABLE
- ADC
DIGITAL FILTER
VIA THE SF SFR.
CHOP
AVERAGE
OUTPUT
AS PART OF THE CHOPPING
WITH ITS PREDECESSOR
IMPLEMENTATION, EACH
SUMMED AND AVERAGED
TO NULL ADC CHANNEL
DATA-WORD OUTPUT
FROM THE FILTER IS
OUTPUT AVERAGE
OFFSET ERRORS.
THE OUPUT WORD FROM THE
THE CONVERSION RESULT.
DIGITAL FILTER IS SCALED
COEFFICIENTS BEFORE
BY THE CALIBRATION
BEING PROVIDED AS
ADuC836
OUTPUT SCALING
SCALING
OUTPUT
3
programmable
RESULT WRITTEN
DIGTAL OUTPUT
TO ADC0H/M/L
SFRS