ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 24

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Auxiliary ADC
The auxiliary ADC is intended to convert supplementary inputs
such as those from a cold junction diode or thermistor.This ADC
is not buffered and has a fixed input range of 0V to 2.5V (assuming
an external 2.5 V reference).The single-ended inputs can be driven
from AIN3, AIN4, or AIN5 pins, or directly from the on-chip
temperature sensor voltage. A block diagram of the auxiliary ADC
is shown in Figure 8.
Analog Input Channels
The primary ADC has four associated analog input pins (labeled
AIN1 to AIN4) that can be configured as two fully differential input
channels. Channel selection bits in the ADC0CON SFR detailed
in Table VI allow three combinations of differential pair selection
as well as an additional shorted input option (AIN2–AIN2).
ADuC836
TEMPERATURE
ON-CHIP
SENSOR
CONVERSION CYCLE. CHOPPING
ANALOG INPUT CHOPPING
THE INPUTS ARE ALTERNATELY
THE MULTIPLEXER IS CONTROLLED
AIN3
AIN4
AIN5
EXTERNAL SINGLE ENDED INPUTS
OR THE ON-CHIP TEMP. SENSOR.
OFFSET AND OFFSET DRIFT
ALLOWS SELECTION OF THREE
A DIFFERENTIAL MULTIPLEXER
VIA THE CHANNEL SELECTION
REVERSED THROUGH THE
YIELDS EXCELLENT ADC
ANALOG MULTIPLEXER
PERFORMANCE.
BITS IN ADC1CON.
MUX
MU
X
CHOP
REFIN(–) REFIN(+)
REFERENCE VOLTAGE IS SELECTED
THE EXTERNAL REFERENCE INPUT
TO THE ADuC836 IS DIFFERENTIAL
DIFFERENTIAL REFERENCE
AND FACILITATES RATIOMETRIC
CIRCUITRY TESTS FOR OPEN OR
VIA THE XREF1 BIT IN ADC1CON.
SHORTED REFERENCE INPUTS.
OPERATION. THE EXTERNAL
STREAM (THE OUTPUT OF WHICH
THE MODULATOR PROVIDES A
HIGH FREQUENCY 1-BIT DATA
REPRESENTS THE SAMPLED
REFERENCE DETECT
THE DUTY CYCLE OF WHICH
IS ALSO CHOPPED) TO THE
ANALOG INPUT VOLTAGE.
Figure 8. Auxiliary ADC Block Diagram
- MODULATOR
DIGITAL FILTER,
MODULATOR
-
- ADC
PROGRAMMABLE
DIGITAL FILTER
–24–
The auxiliary ADC has three external input pins (labeled AIN3
to AIN5) as well as an internal connection to the on-chip tem-
perature sensor. All inputs to the auxiliary ADC are single-ended
inputs referenced to the AGND on the part. Channel selection
bits in the ADC1CON SFR detailed in Table VII allow selection
of one of four inputs.
Two input multiplexers switch the selected input channel to the
on-chip buffer amplifier in the case of the primary ADC and
directly to the - modulator input in the case of the auxiliary
ADC. When the analog input channel is switched, the settling
time of the part must elapse before a new valid word is available
from the ADC.
ENSURES 16 BITS NO MISSING
CODES. THE ENTIRE - ADC
IS CHOPPED TO REMOVE
THE - ARCHITECTURE
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
DRIFT ERRORS.
PROGRAMMABLE DIGITAL
RATE AND BANDWIDTH OF THIS
FILTER ARE PROGRAMMABLE
THE SINC 3 FILTER REMOVES
- ADC
VIA THE SF SFR.
CHOP
FILTER
AVERAGE
OUTPUT
AS PART OF THE CHOPPING
SUMMED AND AVERAGED
WITH ITS PREDECESSOR
IMPLEMENTATION, EACH
TO NULL ADC CHANNEL
OUTPUT AVERAGE
DATA-WORD OUTPUT
FROM THE FILTER IS
OFFSET ERRORS.
DIGITAL FILTER IS SCALED BY
THE OUPUT WORD FROM THE
THE CONVERSION RESULT.
SCALING
OUTPUT
COEFFICIENTS BEFORE
OUTPUT SCALING
BEING PROVIDED AS
THE CALIBRATION
RESULT WRITTEN
TO ADC1H/L SFRs
DIGTAL OUTPUT
REV. A