ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 51

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notice also that direct access to the SCLOCK and SDATA/MOSI
pins is afforded through the SFR interface in I
Therefore, if you are not using the SPI or I
use these two pins to provide additional high current digital outputs.
REV. A
Figure 44. SDATA/MOSI Pin I/O Functional Equivalent
in SPI Mode
Figure 45. SDATA/MOSI Pin I/O Functional Equivalent
in I
BITS
SFR
SPE = 0 (I
(MASTER/SLAVE)
MDO
HARDWARE SPI
MDE
I2CM
Figure 42. SCLOCK Pin I/O Functional Equivalent
in SPI Mode
Figure 43. SCLOCK Pin I/O Functional Equivalent
in I
MDI
2
(MASTER/SLAVE)
HARDWARE SPI
C Mode
HARDWARE I
(SLAVE ONLY)
SPE = 0 (I
2
HARDWARE I
(SLAVE ONLY)
MCO
I
C Mode
BITS
SFR
SPE = 1 (SPI ENABLE)
2
CM
2
C ENABLE)
SPE = 1 (SPI ENABLE)
2
C ENABLE)
REJECTION FILTER
2
REJECTION FILTER
C
2
50ns GLITCH
C
50ns GLITCH
SCHMITT
TRIGGER
Q1
Q3
Q1
Q3
DV
DV
DV
DD
Q1
(OFF)
Q3
DD
2
DD
C functions, you can
Q2 (OFF)
Q4 (OFF)
Q2 (OFF)
Q4 (OFF)
2
C master mode.
Q2
Q4
DV
Q1
(OFF)
Q3
SCLOCK
DD
PIN
SDATA/
Q2
Q4
SCLOCK
MOSI
PIN
PIN
SDATA/
MOSI
PIN
–51–
As shown in Figure 46, the MISO pin in SPI master/slave opera-
tion offers the exact same pull-up and pull-down configuration as
the MOSI pin in SPI slave/master operation.
The SS pin has a weak internal pull-up permanently enabled to
prevent the SS input from floating. This pull-up can be easily
overdriven by an external device to drive the SS pin low.
Read-Modify-Write Instructions
Some 8051 instructions that read a port, read the latch and
others read the pin. The instructions that read the latch rather
than the pins are the ones that read a value, possibly change it,
and then rewrite it to the latch. These are called “read-modify-
write” instructions. which are listed below. When the destination
operand is a port or a port bit, these instructions read the latch
rather than the pin.
ANL
ORL
XRL
JBC
CPL
INC
DEC
DJNZ
MOV PX.Y, C* (Move Carry to Bit Y of Port X)
CLR PX.Y*
SETB PX.Y*
*These instructions read the port byte (all eight bytes), modify the addressed bit
The reason that read-modify-write instructions are directed to
the latch rather than to the pin is to avoid a possible misinter-
pretation of the voltage level of a pin. For example, a port pin
might be used to drive the base of a transistor.When a 1 is written
to the bit, the transistor is turned on. If the CPU then reads the
same port bit at the pin rather than the latch, it will read the base
voltage of the transistor and interpret it as a Logic 0. Reading the
latch rather than the pin will return the correct value of 1.
and then write the new byte back to the latch.
Figure 46. MISO Pin I/O Functional Equivalent
Figure 47. SS Pin I/O Functional Equivalent
(MASTER/SLAVE)
(MASTER/SLAVE)
HARDWARE SPI
HARDWARE SPI
(Logical AND, e.g., ANL P1, A)
(Logical OR, e.g., ORL P2, A)
(Logical EX-OR, e.g., XRL P3, A)
(Jump If Bit = 1 and Clear Bit,
e.g., JBC P1.1, LABEL
(Complement Bit, e.g., CPL P3.0)
(Increment, e.g., INC P2)
(Decrement, e.g., DEC P2)
(Decrement and Jump IFf Not Zero,
e.g.,DJNZ P3, LABEL)
(Clear Bit Y of Port X)
(Set Bit Y of Port X)
DV
DV
DD
DD
MISO
PIN
SS
PIN
ADuC836