ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 45

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPIDAT
Function
SFR Address
Power-On Default Value
Bit Addressable
Depending on the configuration of the bits in the SPICON SFR
shown in Table XXI, the ADuC836 SPI interface will transmit
or receive data in a number of possible modes. Figure 34 shows
all possible ADuC836 SPI configurations and the timing rela-
tionships and synchronization between the signals involved. Also
shown in this figure is the SPI Interrupt bit (ISPI) and how it is
triggered at the end of each byte-wide communication.
REV. A
(CPHA = 0)
(CPHA = 1)
SAMPLE INPUT
SAMPLE INPUT
DATA OUTPUT
DATA OUTPUT
Figure 34. SPITiming, All Modes
(CPOL = 1)
(CPOL = 0)
ISPI FLAG
ISPI FLAG
SCLOCK
SCLOCK
SS
?
MSB BIT 6 BIT 5
SPI Data Register
The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read
data just received by the SPI interface.
F7H
00H
No
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
–45–
SPI Interface—Master Mode
In Master mode, the SCLOCK pin is always an output and gen-
erates a burst of eight clocks whenever user code writes to the
SPIDAT Register. The SCLOCK bit rate is determined by SPR0
and SPR1 in SPICON. It should also be noted that the SS pin
is not used in Master mode. If the ADuC836 needs to assert
the SS pin on an external slave device, a port digital output pin
should be used.
In Master mode, a byte transmission or reception is initiated
by a write to SPIDAT. Eight clock periods are generated via
the SCLOCK pin and the SPIDAT byte being transmitted via
MOSI. With each SCLOCK period, a data bit is also sampled
via MISO. After eight clocks, the transmitted byte will have been
completely transmitted and the input byte will be waiting in the
input shift register. The ISPI flag will be set automatically and an
interrupt will occur if enabled. The value in the shift register will
be latched into SPIDAT.
SPI Interface—Slave Mode
In Slave mode, the SCLOCK is an input. The SS pin must also
be driven low externally during the byte communication. Trans-
mission is also initiated by a write to SPIDAT. In Slave mode,
a data bit is transmitted via MISO and a data bit is received via
MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte will have been completely transmitted and
the input byte will be waiting in the input shift register. The ISPI
flag will be set automatically and an interrupt will occur if enabled.
The value in the shift register will be latched into SPIDAT only
when the transmission/reception of a byte has been completed.
The end of transmission occurs after the eighth clock has been
received, if CPHA = 1 or when SS returns high if CPHA = 0.
ADuC836