ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 71

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PROGRAMMING THE TIMERS
Understanding synchronization across timer domains also
requires that the user code carefully program the timers when
stopping or starting them. The recommended code controls the
timer block when stopping and starting the timers and when
using different clock domains. This can be critical, especially if
timers are enabled to generate an IRQ or FIQ exception; Timer2
is used as an example.
Halting Timer2
When halting Timer2, it is recommended that the IRQEN
bit for Timer2 be masked (using IRQCLR). This prevents
unwanted IRQs from generating an interrupt in the MCU
before the T2CON control bits have been latched in the Timer2
internal logic.
IRQCLR = WAKEUP_TIMER_BIT;
T2CON=0x00;
Starting Timer2
When starting Timer2, it is recommended to first load Timer2
with the required TxLD value. Next, start the timer by setting
the T2CON bits as required. This enables the timer, but only
when the T2CON bits have been latched internally in the
Timer2 clock domain. Therefore, it is advised that a delay of
more than three clock periods (that is, 100 μs for a 32 kHz timer
clock source) be inserted to allow both the T2LD value and the
T2CON value to be latched through the synchronization logic
and reach the Timer2 domain.
After the delay, it is recommended that any (inadvertent)
Timer2 interrupts are now cleared using T2CLRI = 0x00.
Finally, the Timer2 system interrupt can be unmasked by
setting the appropriate bit in the IRQEN MMR. An example
of this code is as follows, with the assumption that Timer2 is
halted:
Example Code
T2LD = 0x1;
T2CON = 0x02CF;
Power
Delay(100us);
ensure T2CON bits take effect
T2CLRI = 0 ;
IRQEN = WAKEUP_TIMER_BIT;
Osc, 32768 prescaler
32.768kHz OSCILLATOR
32.768kHz OSCILLATOR
EXTERNAL 32.768kHz
CLOCK FREQUENCY
WATCH CRYSTAL
LOW POWER
PRECISION
CORE
//Masking interrupts
//Halting the timer
//Reload Timer
//Enable T2—Low
//Include Delay to
//*ClearTimerIrq
//Unmask Timer2
Figure 32. Timer0 Block Diagram
1, 16, 256, OR 32768
IRQ[31:0]
PRESCALAR
Rev. A | Page 71 of 120
TIMER0—LIFETIME TIMER
Timer0 is a general-purpose 48-bit count-up, or a 16-bit count-
up/count-down timer with a programmable prescalar. Timer0
can be clocked from either the core clock, the low power
32.768 kHz oscillator, the precision 32.768 kHz oscillator, or an
external 32.768 kHz crystal with a prescalar of 1, 16, 256, or
32,768. This gives a minimum resolution of 48.83 ns when the
core is operating at 20.48 MHz, and with a prescalar of 1.
In 48-bit mode, Timer0 counts up from zero. The current
counter value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or count down. A 16-bit
value can be written to T0LD that is loaded into the counter.
The current counter value can be read from T0VAL0. Timer0
has a capture register (T0CAP) that can be triggered by a selected
IRQ source initial assertion. Once triggered, the current timer
value is copied to T0CAP, and the timer keeps running. This
feature can be used to determine the assertion of an event with
more accuracy than by servicing an interrupt alone.
Timer0 reloads the value from T0LD either when Timer0
overflows, or immediately when T0CLRI is written.
The Timer0 interface consists of the following six MMRs:
•
•
•
•
•
16-BIT UP/DOWN COUNTER
CAPTURE
T0LD: 16-bit register that holds the 16-bit value that is
loaded into the counter. Available only in 16-bit mode
T0CAP: 16-bit register that holds the 16-bit value captured by
an enabled IRQ event. Available only in 16-bit mode.
T0VAL0 and T0VAL1: 16-bit and 32-bit registers that hold
the 16 least significant bits (LSBs) and 32 most significant bits
(MSBs), respectively. T0VAL0 and T0VAL1 are read only.
In 16-bit mode, 16-bit T0VAL0 is used. In 48-bit mode, both
the 16-bit T0VAL0 and 32-bit T0VAL1 are used.
T0CLRI: 8-bit register. Writing any value to this register
clears the interrupt. Available only in 16-bit mode.
T0CON: configuration MMR described in Table 54.
48-BIT UP COUNTER
16-BIT LOAD
TIMER0
VALUE
TIMER0 IRQ
ADuC7032-8L