ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 25

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FLASH/EE MEMORY AND THE ADUC7032-8L
The ADuC7032-8L incorporates Flash/EE memory technology
on-chip to provide the user with nonvolatile, in-circuit repro-
grammable memory space.
Like EEPROM, Flash memory can be programmed in-system
at the byte level, although it must first be erased, the erase being
performed in page blocks. Thus, Flash memory is often and
more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit program-
mability, high density, and low cost. Incorporated in the
ADuC7032-8L, Flash/EE memory technology allows the user
to update program code space in-circuit, without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
Flash/EE Memory
The total 96 kB of Flash/EE memory is organized as 48 kB × 16
bits. Of the 96 kB, 94 kB is user space, and 2 kB is reserved for
boot loader/kernel space. The page size of this Flash/EE memory
is 512 bytes. Typically, it takes the Flash/EE controller 20 ms to
erase a page, and 50 μs to write a 16-bit word. These Flash/EE
timings are independent of the MCU core clock.
There is 94 kB of Flash/EE memory available to the user as code
and nonvolatile data memory. There is no distinction between
data and program, because ARM code shares the same space.
The real width of the Flash/EE memory is 16 bits, which means
that in ARM mode (32-bit instruction), two accesses to the
Flash/EE are necessary for each instruction fetch. When operating
at speeds less than 20.48 MHz, the Flash/EE memory controller
can transparently fetch the second 16-bit halfword (part of the
32-bit ARM operation code) within a single core clock period.
Therefore, for speeds less than 20.48 MHz (that is, CD > 0), it is
recommended that ARM mode be used. For 20.48 MHz
operation (that is, CD = 0), it is recommended that Thumb
mode be used.
The Flash/EE memory is physically located at Address 0x80000.
Upon a hard reset, it is logically mapped to 0x00000000. The
factory default contents of all Flash/EE memory locations is
0xFF. Flash/EE can be read in 8-, 16-, and 32-bit segments and
written in segments of 16 bits. The Flash/EE is rated for 10,000
endurance cycles. This rating is based on the number of times
that each individual halfword (16-bit location) is cycled, that is,
erased and programmed. A redundancy scheme can be imple-
mented in software to ensure greater than 10,000 cycles of
endurance.
The user can also write data variables to the Flash/EE memory
during run-time code execution, for example, for storing
diagnostic battery parameter data.
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It is possible to write to a single 16-bit location only twice between
erases; that is, it is possible to walk bytes, not bits. If a location
is written to more than twice, the contents of the Flash/EE page
may be corrupted.
The 94 kB of Flash/EE memory can be programmed in-circuit,
using a serial download mode via the LIN interface or the
integrated JTAG port.
Serial Downloading (In-Circuit Programming)
The ADuC7032-8L facilitates code download via the LIN pin.
JTAG Access
The ADuC7032-8L features an on-chip JTAG debug port to
facilitate code download and debug.
FLASH/EE CONTROL INTERFACE
The access to and control of the Flash/EE memory on the
ADuC7032-8L is managed by an on-chip memory controller.
The controller manages the Flash/EE memory as two separate
blocks (Block 0 and Block 1).
Block 0 consists of the 32 kB Flash/EE memory mapped from
0x00090000 to 0x00097FFF (including the 2 kB kernel space
that is reserved at the top of this block).
Block 1 consists of the 6 kB Flash/EE memory mapped from
0x00080000 to 0x0008FFFF.
Note that the MCU core can continue to execute code from one
memory block while an active erase or program cycle is being
carried out on the other block. If a command operates on the
same block as the code currently executing, the core is halted
until the command is completed. This also applies to code
execution.
User code, LIN, and JTAG programming use the Flash/EE
control interface, which consists of the following MMRs:
•
•
•
•
•
•
FEExSTA (x = 0 or 1): read-only register that reflects the
status of the Flash/EE memory control interface
FEExMOD (x = 0 or 1): sets the operating mode of the
Flash/EE memory control interface
FEExCON (x = 0 or 1): 8-bit command register;
the commands are interpreted as described in Table 14.
FEExDAT (x = 0 or 1): 16-bit data register
FEExADR (x = 0 or 1): 16-bit address register
FEExSIG (x = 0 or 1): holds the 24-bit code signature
as a result of the signature command being initiated
ADuC7032-8L