ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 27

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Command Sequence for Executing a Mass Erase
Because of the significance of the mass erase command,
a specific code sequence must be executed to initiate this
operation.
1.
2.
3.
4.
Command Sequence Example
The command sequence for executing a mass erase is illustrated in the following example:
Int a = FEExSTA;
FEExMOD = 0x08;
FEExADR = 0xFFC3;
FEExDAT = 0x3CFF;
FEExCON = 0x06;
while (FEExSTA & 0x04){}
FEE0STA and FEE1STA Registers
Name: FEE0STA and FEE1STA
Address: 0xFFFF0E00 and 0xFFFF0E80
Default Value (Both Registers): 0x20
Access: Read only
Function: These 8-bit read-only registers can be read by user code and reflect the current status of the Flash/EE memory controllers.
Table 15. FEE0STA and FEE1STA MMR Bit Designations
Bit
15 to 4
3
2
1
0
1
FEE0ADR and FEE1ADR Registers
Name: FEE0ADR and FEE1ADR
Address: 0xFFFF0E10 and 0xFFFF0E90
Default Value: Nonzero (FEE0ADR), 0x0000 (FEE1ADR)
Access: Read/write
Function: This 16-bit register dictates the address acted upon by any Flash/EE command executed via FEExCON.
FEE0DAT and FEE1DAT Registers
Name: FEE0DAT and FEE1DAT
Address: 0xFFFF0E0C and 0xFFFF0E8C
Default Value (Both Registers): 0x0000
Access: Read/write
Function: This 16-bit register contains the data either read from or to be written to the Flash/EE memory controllers.
x is 0 or 1 to designate Flash/EE Block 0 or Flash/EE Block 1.
Set Bit 3 in FEExMOD.
Write 0xFFC3 in FEExADR.
Write 0x3CFF in FEExDAT.
Run the mass erase command 0x06 in FEExCON.
Description
Not Used. These bits are not used and are always read as 0.
Flash Interrupt Status Bit.
Flash/EE Controller Busy.
Command Fail.
Command Successful.
Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the
FEExMOD register is set.
Cleared automatically when the FEExSTA register is read by user code.
Set automatically when the Flash/EE controller is busy.
Cleared automatically when the controller is not busy.
Set automatically when a command written to FEExCON completes unsuccessfully.
Cleared automatically when the FEExSTA register is read by user code.
Set automatically by MCU when a command is completed successfully.
Cleared automatically when the FEExSTA register is read by user code.
1
// Ensure FEExSTA is cleared
// Mass-Erase command
// Wait for command to finish
Rev. A | Page 27 of 120
To run the mass-erase command via FEE0CON, write protection
on the lower 64 kB must be disabled; that is, FEE1HID and
FEE1PRO are set to 0xFFFFFFFF. This is accomplished by first
removing the protection or by erasing the lower 64 kB first.
ADuC7032-8L