ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 102

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7032-8L
SPI Control Register
Name: SPICON
Address: 0xFFFF0A10
Default Value: 0x0000
Access: Read/write
Function: This 16-bit MMR configures the serial peripheral interface.
Table 89. SPICON MMR Bit Designations
Bit
15 to 13
12
11
10
9
8
7
6
5
4
3
2
1
0
Description
Reserved. Should be written as 0.
Continuous Transfer Enable.
Loop Back Enable.
Slave Output Enable.
Slave Select Input Enable.
SPIRX Overflow Overwrite Enable.
SPITX Underflow Mode.
Transfer and Interrupt Mode (Master Mode).
LSB First Transfer Enable Bit.
Reserved. Should be written as 0.
Serial Clock Polarity Mode Bit.
Serial Clock Phase Mode Bit.
Master Mode Enable Bit.
SPI Enable Bit.
Set by user to enable continuous transfer. In master mode the transfer continues until no valid data is available in the SPITX
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the
Set by user to enable slave output.
Cleared by user to disable slave output.
register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty.
SPITX register, a new transfer is initiated after a stall period.
Set by user to connect MISO to MOSI and test software.
Cleared by user to normal mode.
Set by user in master mode to enable the output.
Set by user. The valid data in the RX register is overwritten by the new serial byte received.
Cleared by user. The new serial byte received is discarded.
Set by user to transmit the previous data.
Cleared by user to transmit 0.
Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs when SPITX is empty.
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs when SPIRX is full.
Set by user. The LSB is transmitted first.
Cleared by user. The MSB is transmitted first.
Set by user. The serial clock idles high.
Cleared by user. The serial clock idles low.
Set by user. The serial clock pulses at the beginning of each serial bit transfer.
Cleared by user. The serial clock pulses at the end of each serial bit transfer.
Set by user to enable master mode.
Cleared by user to enable slave mode.
Set by user to enable the SPI.
Cleared to disable the SPI.
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