ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 32

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7032-8L
ADUC7032-8L KERNEL
The ADuC7032-8L features an on-chip kernel resident in the top
2 kB of the Flash/EE code space. After any reset event, this kernel
copies the factory-calibrated data from the manufacturing data
space into the various on-chip peripherals. The peripherals
calibrated by the kernel are
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User MMRs that can be modified by the kernel and differ from
their POR default values are
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PSM (power supply monitor)
Precision oscillator
Low power oscillator
REG_AVDD/REG_DVDD
Low power voltage reference
Normal mode voltage reference
Current ADC (offset and gain)
Voltage ADC (offset and gain)
Temperature ADC (offset and gain)
R0 to R15
GP0CON/GP2CON
SYSCHK
ADCMDE/ADC0CON
FEE0ADR/FEE0CON/FEE0SIG
HVDAT/HVCON
HVCFG0/HVCFG1
T3LD
Rev. A | Page 32 of 120
The ADuC7032-8L also features an on-chip LIN downloader.
Figure 13 is a flow chart showing the execution of the kernel.
The current revision of the kernel can be derived from SYSSER1,
as described in Table 96.
For the duration of kernel execution, the watchdog timer is
active with a timeout period of 30 ms, which ensures that the
ADuC7032-8L is reset if an error occurs in the kernel. The
watchdog timer is disabled once the kernel code is exited.
Normal kernel execution time, excluding LIN download, is
approximately 5 ms. It is possible to enter and leave LIN download
mode only via a reset.
SRAM is not modified during normal kernel execution. SRAM
is modified during LIN download kernel execution.
Note that, even with NTRST = 0, user code is not executed unless
Address 0x14 contains either 0x27011970 or the checksum of
Page 0, excluding Address 0x14. If Address 0x14 does not contain
this information, user code is not executed and LIN download
mode is entered.
With NTRST = 1, user code is always executed.
During kernel execution, JTAG access is disabled.