ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 49

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADC Filter Register
Name: ADCFLT
Address: 0xFFFF0518
Default Value: 0x0007
Access: Read/write
Function: The ADC filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs.
Note: If ADCFLT is modified, the current, voltage, and temperature ADCs are reset. An additional time of 60 μs per enabled ADC is
required before the first ADC result is available.
Table 40. ADCFLT MMR Bit Designations
Bit
15
14
13 to 8
7
6 to 0
1
2
Note that due to limitations on the digital filter internal datapath,
there are some limitations on the combinations of SF (Sinc3
decimation factor) and AF (averaging factor) that can be used
to generate a required ADC output rate. This restriction limits
the minimum ADC update to 4 Hz in normal power mode or
to 1 Hz in low power mode. If all three ADCs are enabled, then
the minimum value of SF written by user code must be 1.
This is valid for all SF values ≤ 125. For SF = 126, f
For information on calculating the f
Description
Chop Enable.
Running Average.
Averaging Factor (AF). The value written to these bits is used to implement a programmable first-order Sinc3 post filter. The
averaging factor can further reduce ADC noise at the expense of output rate, as described in the Sinc3 decimation factor bits
(Bit 6 to Bit 0).
Sinc3 Modify.
Sinc3 Decimation Factor (SF). The value (SF) written in these bits controls the oversampling (decimation factor) of the Sinc3
filter. The output rate from the Sinc3 filter is given by f
(AF = averaging factor).
Set by user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low offset errors and drift, but
the ADC output rate is reduced by a factor of 3 if AF = 0 (see Sinc3 decimation factor bits, Bit 6 to Bit 0). If AF ≠ 0, then the ADC
output update rate is the same with chop on or off. When chop is enabled, the settling time is two output periods.
Set by user to enable a running average-by-2 function, reducing ADC noise. This function is automatically enabled when
chopping is active. It is an optional feature when chopping is inactive and, if enabled (when chopping is inactive), it does
not reduce ADC output rate but increases the settling time by one conversion period.
Cleared by user to disable the running average function.
Set by user to modify the standard Sinc3 frequency response to increase the filter stop-band rejection by 5 dB approximate.
This is achieved by inserting a second notch (NOTCH2) at
in the response.
ADC
for SF (other than 126 and 127) and AF values, see Table 41.
1, 2
ADC
is forced to 60 Hz. For SF = 127, f
Rev. A | Page 49 of 120
ADC
= (512,000/([SF+1] × 64)) Hz when the chop bit (Bit 15) = 0 and AF = 0
f
NOTCH2
ADC
is forced to 50 Hz.
In low power mode and low power plus mode, the ADC is driven
directly by the low power oscillator, or 131 kHz, and not 512 kHz.
All f
For optimal ADC performance, SF should be increased before
AF is used.
= 1.333 × f
ADC
calculations should be divided by 4 (approximate).
NOTCH
where f
NOTCH
is the location of the first notch
ADuC7032-8L