ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 62

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7032-8L
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs, PLLCON and POWCON;
and the status of the PLL is indicated by PLLSTA. PLLCON
controls the operating mode of the clock system, and POWCON
controls the core clock frequency and the power-down mode.
PLLSTA indicates the presence of an oscillator on the XTAL1
pin, the PLL lock status, and the PLL interrupt.
It is recommended that, before the ADuC7032-8L is powered
down, the clock source for the PLL be switched to the low
power 131 kHz oscillator to reduce wake-up time. The low
power oscillator is always active.
When the ADuC7032-8L wakes up from power-down, the
MCU core begins executing code once the PLL begins oscil-
lating. This occurs before the PLL has locked to a frequency
of 20.48 MHz. To ensure the Flash/EE memory controller is
executing with a valid clock, the controller is driven with a PLL
output divided by eight clock source while the PLL is locking.
Writing to the POWCON and the PLLCON MMRs
An example of writing to both the POWCON and PLLCON MMRs follows:
POWKEY0 = 0x01;
POWCON
POWKEY1 = 0xF4;
iA1 × iA2;
PLLKEY0 = 0xAA;
PLLCON
PLLKEY1 = 0x55;
iA1 × iA2;
PLLSTA Register
Name: PLLSTA
Address: 0xFFFF0400
Default Value: 0x02
Access: Read only
Function: This 32-bit register allows user code to monitor the lock state of the PLL and the status of the external crystal.
Table 45. PLLSTA MMR Bit Designations
Bit
31 to 3
2
1
0
= 0x00;
= 0x0;
Description
Reserved. Should be written as 0s.
XTAL Clock, Read Only. This is a live representation of the current logic level on XTAL1. This allows the user to check if
an external clock source is present. If present, this bit alternates high and low at a frequency of 32.768 kHz.
PLL Lock Status Bit, Read Only.
PLL Interrupt.
Set when the PLL is locked and outputting 20.48 MHz.
Clear when the PLL is not locked and outputting an F core/8 clock source.
Set if the PLL lock status bit signal goes low.
Cleared by writing 1 to this bit.
// POWCON KEY
// Full power-down
// POWCON KEY
// dummy cycle to clear the pipe line, where iA1 and iA2 are defined as longs
// and are not 0
// PLLCON KEY
// Switch to low power oscillator
// dummy cycle to prevent Flash/EE access during clock change
// PLLCON KEY
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Once the PLL locks, the PLL output is switched from the PLL
output divided by eight to the locked PLL output.
If user code requires an accurate PLL output, user code must
poll the lock bit (PLLSTA[1]) after wake-up and before
resuming normal code execution.
The PLL is locked and executing user code within 2 ms if the
PLL is clocked from an active clock source (for example, a low
power 131 kHz oscillator) after waking up.
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PLLCON: protected MMR with two 32-bit keys: PLLKEY0,
a prewrite key; and PLLKEY1, a postwrite key.
PLLKEY0 = 0x000000AA
PLLKEY1 = 0x00000055
POWCON: protected MMR with two 32-bit keys:
POWKEY0, a prewrite key; and POWKEY1, a postwrite key.
POWKEY0 = 0x00000001
POWKEY1 = 0x000000F4