ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 43

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bit
15
14
13
12
11
10
9
8
7
6
5
ADC MMR INTERFACE
The ADC is controlled and configured via a number of MMRs
that are described in detail on the following pages.
All bits defined in the top eight MSBs (Bit 8 to Bit 15) of the
ADCSTA MMR (see Table 35) are used as flags only and do not
generate interrupts. All bits defined in the lower eight LSBs (Bit
0 to Bit 7) of this MMR are logic OR’ e d to produce a single ADC
interrupt to the MCU core.
In response to an ADC interrupt, user code should interrogate
the ADCSTA MMR to determine the source of the interrupt.
Each ADC interrupt source can be individually masked via the
ADCMSKI MMR, as described in the ADC Interrupt Source
Enable Register section.
ADC Status Register
Name: ADCSTA
Address: 0xFFFF0500
Default Value: 0x0000
Access: Read only
Function: This register holds general status information related to the mode of operation or current status of the ADuC7032-8L ADCs.
Table 35. ADCSTA MMR Bit Designations
Description
ADC Voltage Conversion Error.
ADC Current Conversion Error.
Not Used. Reserved for future functionality and should not be monitored by user code.
Not Used. Reserved for future functionality and should not be monitored by user code.
ADC FIFO Error Flag.
ADC FIFO Empty Flag.
ADC FIFO Full Flag.
Accumulator Comparator Threshold Exceeded.
Not Used. Reserved for future functionality and should not be monitored by user code.
ADC Calibration Status.
ADC Temperature Conversion Error.
Set automatically in hardware to indicate that an ADC calibration cycle has been completed.
Cleared after ADCMDE is written to.
Set automatically in hardware to indicate that a temperature conversion overrange or underrange has occurred. The conversion
result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register.
Set automatically in hardware to indicate that a voltage conversion overrange or underrange has occurred. The conversion result
is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
Set automatically in hardware to indicate that a current conversion overrange or underrange has occurred. The conversion result is
clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) current conversion result is written to the ADC0DAT register.
Set to 1 automatically to indicate that the FIFO has overflowed. This bit does not cause an interrupt but is latched high and can be
cleared only by disabling the FIFO or reconfiguring the ADC.
Reads 0 if the FIFO is disabled or if the FIFO has not overflowed.
Set to 1 automatically to indicate the ADC FIFO is empty. It is a flag bit only and cannot generate an interrupt.
Reads 0 if the ADC FIFO is disabled.
Set to 1 automatically to indicate the ADC FIFO is full. Any subsequent I-ADC and V-ADC conversion results cause an overflow and
corrupt the ADC FIFO.
Cleared by disabling the FIFO or reconfiguring the ADC.
Indicates that the absolute value of the current channel accumulator has exceeded the programmed threshold.
Cleared by disabling the accumulator comparator function in ADCCFG[6:5] or by reconfiguring the ADC.
Rev. A | Page 43 of 120
All ADC result-ready bits are cleared by a read of the ADC0DAT
MMR. If the current channel ADC is not enabled, all ADC
result-ready bits are cleared by a read of the ADC1DAT or
ADC2DAT MMRs.
To ensure that I-ADC, V-ADC, and T-ADC conversion data is
synchronous, user code should first read the ADC2DAT/
ADC1DAT MMRs and then the ADC0DAT MMR. New ADC
conversion results are not written to the ADCxDAT MMRs
unless the respective ADC result-ready bits are first cleared.
The only exception to this rule is data conversion result updates
when the ARM core is powered down. In this mode, ADCxDAT
registers always contain the most recent ADC conversion results,
even though the ready bits have not been cleared.
ADuC7032-8L