ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 55

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

It is worth emphasizing that the I-ADC , V-ADC, and T-ADC
channels can be configured to initiate periodic, normal power
mode, high accuracy, single conversion cycles before returning
to ADC full power-down mode. This flexibility is facilitated
under full MCU control via the ADCMDE MMR and ensures
that continuous periodic monitoring of battery current, voltage,
and temperature settings is feasible, while ensuring the average
dc current consumption is minimized.
In ADC normal mode, the PLL must not be powered down.
ADC Low Power Mode
In ADC low power mode, the I-ADC is enabled in a reduced
power and reduced accuracy configuration. The ADC modulator
clock is driven directly from the on-chip 131 kHz low power
oscillator, which allows the ADC to be configured at update
rates as low as 1 Hz (ADCFLT). The gain of the ADC in this
mode is fixed at 128.
All of the ADC peripheral functions (result counter, digital
comparator, and accumulator) described previously in normal
power mode can still be enabled in low power mode.
Typically, in low power mode, only the I-ADC is configured to
run at a low update rate, continuously monitoring battery current.
The MCU is in power-down mode and is powered up only when
the I-ADC interrupts the MCU. This happens after the I-ADC
detects a current conversion or an accumulated current value
that has risen beyond a preprogrammed threshold, setpoint,
or a set number of conversions.
It is also possible to select either the ADC normal mode voltage
reference or the ADC low power mode voltage reference via
ADCMDE[5].
ADC Low Power Plus Mode
In low power plus mode, the I-ADC channel is enabled in a
mode almost identical to low power mode (ADCMDE[4:3]).
However, in this mode, the I-ADC gain is fixed at 512, and the
ADC consumes an additional 200 μA (approximate) to yield
improved noise performance relative to the low power mode
setting.
Rev. A | Page 55 of 120
Again, all of the ADC peripheral functions (result counter,
digital comparator, and accumulator) described in the ADC
Normal Power Mode section can still be enabled in low power
plus mode.
As in low power mode, only the I-ADC is configured to run at
a low update rate, continuously monitoring battery current. The
MCU is in power-down mode and powers up only when the
I-ADC interrupts the MCU. This happens after the I-ADC
detects a current conversion result, or an accumulated current
value has risen beyond a preprogrammed threshold or setpoint.
It is also possible to select either the ADC precision voltage
reference or the ADC low power mode voltage reference via
ADCMDE[5].
ADC Sinc3 Digital Filter Response
The overall frequency response on all of the ADuC7032-8L
ADCs is dominated by the low-pass filter response of the on-
chip Sinc3 digital filters. The Sinc3 filters are used to decimate
the ADC Σ-Δ modulator output data bit stream to generate a
valid 16-bit data result. The digital filter response is identical for
all ADCs and is configured via the 16-bit ADC filter (ADCFLT)
register that determines the overall throughput rate of the
ADCs. The noise resolution of the ADCs is determined by the
programmed ADC throughput rate. In the case of the current
channel ADC, the noise resolution is determined by throughput
rate and selected gain.
The overall frequency response and the ADC throughput is
dominated by the configuration of the Sinc3 filter decimation
factor (SF) bits (ADCFLT[6:0]) and the averaging factor (AF)
bits (ADCFLT[13:8]). Due to limitations on the digital filter
internal datapath, there are some limitations on the allowable
combinations of SF (Sinc3 decimation factor) and AF (averaging
factor) that can be used to generate a required ADC output rate.
This restriction limits the minimum ADC update to 4 Hz in
normal power mode or 1 Hz in low power mode. The calcula-
tion of the ADC throughput rate is detailed in Table 40, the
ADCFLT MMR bit designations table, with some examples
in Table 41. The restrictions on allowable combinations of AF
and SF values are outlined in Table 42.
ADuC7032-8L