aduc7032 Analog Devices, Inc., aduc7032 Datasheet
aduc7032
Available stocks
Related parts for aduc7032
aduc7032 Summary of contents
Page 1
... MUX BUF ADC 2xTIMERS WDT W/U TIMER PRECISION TEMP REFERENCE SENSOR Figure 1: ADuC7032 Functional Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 Precision Battery Sensor ADuC7032 MEMORY RESET 96KB FLASH 6KB RAM 128B ADC FIFO PRECISION ...
Page 2
... Preliminary Technical Data TABLE OF CONTENTS TABLE OF CONTENTS................................................... 2 ADUC7032 DATASHEET TABLES................................. 5 ADUC7032 DATASHEET FIGURES .............................. 7 ADUC7032SPECIFICATIONS ........................................ ............................................ 8 LECTRICAL PECIFICATIONS T S ................................................. 15 IMING PECIFICATIONS SPI Timing Specifications........................................... 15 LIN Timing Specifications .......................................... 19 SPECIFICATION TERMINOLOGY............................. 21 ABSOLUTE MAXIMUM RATINGS ............................ ........................................................... 22 RDERING UIDE ESD Caution............................................................... 22 PIN FUNCTION DESCRIPTIONS ............................... 23 ADUC7032 GENERAL DESCRIPTION ...
Page 3
... V IGH OLTAGE UART SERIAL INTERFACE....................................... 106 B AUD RATE GENERATION Normal 450 UART baud rate generation. ................ 106 ADuC7032 Fractional divider: ................................ 106 UART REGISTER DEFINITION UART TX Register:.................................................. 107 UART RX Register:.................................................. 107 UART Divisor Latch Register 0:............................... 107 UART Divisor Latch Register 1:............................... 107 UART Control Register 0: ....................................... 108 UART Control Register 1: ...
Page 4
... Preliminary Technical Data System Serial ID Register 0: .................................... 125 System Serial ID Register 1: .................................... 126 System Kernel Checksum: ........................................ 126 System Identification FEE0ADR: .............................127 OUTLINE DIMENSIONS.............................................128 Rev. PrD | Page 4 of 128 ADuC7032 ...
Page 5
... Preliminary Technical Data ADUC7032 DATASHEET TABLES Table 1 : ADUC7032—SPECIFICATIONS Table 2 : SPI Master Mode Timing (PHASE Mode = 1) Table 3 : SPI Master Mode Timing (PHASE Mode = 0) Table 4 : SPI Slave Mode Timing (PHASE Mode = 1) Table 5 : SPI Slave Mode Timing (PHASE Mode = 0) Table 6. Absolute Maximum Ratings (T ...
Page 6
... Table 83 : LHSCON1 MMR Bit Descriptions Table 84 : SYSSER0 MMR Bit Descriptions Table 85: SYSSER1 MMR Bit Descriptions 108 Table 86: FEE0ADR System Identification MMR Bit Descriptions 109 109 Rev. PrD | Page 6 of 128 ADuC7032 110 110 111 112 112 113 114 116 117 ...
Page 7
... Figure 24 : Typical Digital Filter Response at FADC=4Hz, (ADCFLT = 0xBF1D) ............................................................63 Figure 25 : Typical Digital Filter Response at FADC=1Hz, (ADCFLT = 0xBD1F..............................................................63 Figure 26: Typical Power-On Cycle ..............................................67 Figure 27: ADuC7032 System Clock Generation .......................68 Figure 28 : Example OSC0TRM Calibration Routine................72 Figure 29: Interrupt Structure .......................................................76 Figure 30 : Timer 0 block diagram................................................78 Figure 31 : Timer 1 Block Diagram ..............................................80 Figure 32 : Timer 2 block diagram ...
Page 8
... Includes Resistor Mismatch Drift 1, 15 Output Noise 4Hz Update Rate 10Hz Update Rate 1KHz Update Rate 8KHz Update Rate Table 1 : ADUC7032—SPECIFICATIONS = 10.24MHz driven from external 32.768kHz watch crystal or on-chip CORE = -40°C to 105C, unless otherwise noted 10Hz, Gain=128 ADC = 1Hz, Gain=128 ...
Page 9
... REF Initial Accuracy Measured Initial Accuracy Using ADCREF, measured Temperature Coefficient =19.84uV 16 =1.2V REF 35° 35° 35°C A Rev. PrD | Page 9 of 128 ADuC7032 Min Typ Max 16 ±10 ±60 -10 ±3 + 0.03 -0.2 ±0.06 +0.2 3 7.5 11.25 -200 +300 ±1.2 ± ...
Page 10
... Input Pull-up Current Input (Low Input Capacitance Input Leakage Current NTRST Only :Input (Low Input Pull-down Current NTRST Only : Input (High) = REG_DVDD pin DD pin DD pin DD = 85°C J Rev. PrD | Page 10 of 128 ADuC7032 Min Typ Max ±3 ±2 2.85 3.0 3.15 ...
Page 11
... Driver Off ; 7.0V < V LIN_PAS_REC I 1 Input Leakage V LIN_PAS_DOM Min 2.0 1.7 -6 -1.2 0.160 1000 BAT BAT (MAX) < 18V ; -0.7V BUS DD LIN = 0V -1 LIN Rev. PrD | Page 11 of 128 ADuC7032 Typ Max Unit 0 0 131.072 kHz 3 % 131.072 kHz 1.2 % 10.24 20.48 MHz msec 25 msec ...
Page 12
... BUS BUS 1nF||1k ; 6.8nF|| 660 ; 10nF || 500 = 7V MIN = 7V MIN = 7V MIN || BUS BUS 1nF||1k ; 6.8nF|| 660 ; 10nF || 500 = 18V BAT = 7V BAT = 18V BAT = 7V BAT Rev. PrD | Page 12 of 128 ADuC7032 Min Typ Max -1 1 0.4V DD 0.6V DD 0.475V 0.5 V 0.525V 0.175V DD 1.2 2 0.6 0 ...
Page 13
... BIT TH = 0..284 * V REC(MIN) BAT TH = 0.422 * V DOM(MIN) BAT V = 7.0V…18V 50µs SUP BIT BUS_REC(MAX) BIT = 1kOhm 91nF 39Ohms L BUS LIMIT Rev. PrD | Page 13 of 128 ADuC7032 Min Typ Max 0.396 0.581 4.6 1.2 1.3 140 150 160 50 25 3.5 18 2.5 2.6 2 ...
Page 14
... Typical, additional supply current consumed during Flash memory program and erase cycles is 7mA and 5mA respectively. =1KHz, typical rms noise at the ADC input is 7.5uV, scaled by the attenuator (24) yields these ADC =5mA), and REG_AVDD (I =1mA) SOURCE SOURCE Rev. PrD | Page 14 of 128 ADuC7032 Min Typ Max 520 700 120 300 ...
Page 15
... DAV DF DR MSB BITS 6 – 1 MSB IN BITS 6 – DSU DHD Figure 2. SPI Master Mode Timing (PHASE Mode = 1) Rev. PrD | Page 15 of 128 ADuC7032 Typ Max (SPIDIV + 1) × t HCLK (SPIDIV + 1) × t HCLK LSB LSB IN Unit ...
Page 16
... MSB BITS 6 – 1 MSB IN BITS 6 – DSU DHD Figure 3. SPI Master Mode Timing (PHASE Mode = 0) Rev. PrD | Page 16 of 128 Min Typ (SPIDIV + 1) × t HCLK (SPIDIV + 1) × t HCLK LSB LSB IN ADuC7032 Max Unit ...
Page 17
... DAV DF DR MSB BITS 6 – 1 MSB IN BITS 6 – DSU DHD Figure 4. SPI Slave Mode Timing (PHASE Mode = 1) Rev. PrD | Page 17 of 128 ADuC7032 Typ Max (SPIDIV + 1) × t HCLK (SPIDIV + 1) × t HCLK t SFS LSB LSB IN Unit ns ns ...
Page 18
... BITS 6 – 1 MSB IN BITS 6 – DSU DHD Figure 5 : SPI Slave Mode Timing (PHASE Mode = 0) Rev. PrD | Page 18 of 128 Min Typ (SPIDIV + 1) × t HCLK (SPIDIV + 1) × t HCLK t SFS LSB LSB IN ADuC7032 Max Unit ...
Page 19
... Preliminary Technical Data LIN Timing Specifications Figure 6 : LIN V1.3 Timing Specification Rev. PrD | Page 19 of 128 ADuC7032 ...
Page 20
... OF RECEIVING NODE BIT BIT t t LIN_DOM (MAX) LIN_REC (MIN LIN_DOM (MIN) LIN_REC (MAX RX_PDF RX_PDR t RX_PDR Figure 7 : LIN V2.0 Timing Specification Rev. PrD | Page 20 of 128 ADuC7032 t BIT THRESHOLDS OF RECEIVING NODE 1 LIN BUS THRESHOLDS OF RECEIVING NODE 2 t RX_PDF ...
Page 21
... The peak-to-peak noise can be used to calculate the ADC (Noise Free, Code) Resolution for which there will be no code flicker within a 6.6-Sigma limit as defined by the following equation Noise Free Code Resolution = Log Peak Noise) Bits Rev. PrD | Page 21 of 128 ADuC7032 (Full-Scale Range / RMS Noise) Bits 2 (Full-Scale Range / Peak to 2 ...
Page 22
... REG_DV +0.3 DD -0.3V to REG_AV + 0.3 DD -0.3V to REG_AV +0.3 DD ± 4KV ± 2KV 125°C 150°C 130°C 260°C Package Description Rev. PrD | Page 22 of 128 ADuC7032 ...
Page 23
... JTAG Test Mode Select. This Mode Select input pin is one of the standard 5 I pin JTAG debug port on the part. TMS is an input pin only and has an internal weak pull-up resistor. If not being used this pin can be left unconnected Rev. PrD | Page 23 of 128 ADuC7032 ...
Page 24
... I/O unconnected. GPIO4 is can also be configured to output a 2.56MHz clock No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally Rev. PrD | Page 24 of 128 ADuC7032 ...
Page 25
... This pin is reserved for HV-IO Output only functionality. This pin should connected externally to the IO_VSS ground reference S Ground Reference for High Voltage I/O Pins I/O LIN Serial Interface Input/Output Pin Rev. PrD | Page 25 of 128 ADuC7032 ...
Page 26
... A Flash/EE memory based ARM7 microcontroller (MCU) is also integrated on-chip and is used both to pre-process the acquired battery variables, and to manage communications from the ADuC7032 to the main Electronic Control Unit (ECU) via a Local Interconnect Network (LIN) interface, which is integrated on-chip. Both the MCU and the ADC sub-system can be individually configured to operate in normal or flexible power-saving modes of operation ...
Page 27
... RAM area, and descends, using the area as required. A separate stack is defined for each of the exceptions. The size of each stack is user configurable and is dependent on the target application. On the ADuC7032 the stack begins at 0x000417FC and descends. Whilst programming using high level languages, such may be possible to ensure that the stack does not overflow ...
Page 28
... MEMORY ORGANISATION The ARM7, a Von Neumann architecture, MCU core sees memory as a linear array byte locations. As shown in Figure 11, the ADuC7032 maps this into 4 distinct user areas namely, a re-mappable memory area, an SRAM area, a Flash/EE area and a Memory Mapped Register (MMR) area. ...
Page 29
... MMR, which is located at 0xFFFF0220. To revert Flash/EE to 0x00000000, bit zero of SYSMAP0 is cleared. It may be desirable to remap RAM to 0x00000000 to optimize the interrupt latency of the ADuC7032, as code may be run in full 32bit ARM mode and at the maximum core speed. It should be noted that when an exception occurs, the core will default to ARM mode ...
Page 30
... Preliminary Technical Data ADUC7032 RESET There are four kinds of reset: external reset, Power-on-reset, watchdog reset and software reset. The RSTSTA register indicates the source of the last reset and can also be written by user code to initiate a software reset event. The bits in this register can be cleared to ‘ ...
Page 31
... FLASH/EE MEMORY CONTROL INTERFACE The access to and control of the Flash/EE memory on the ADuC7032 is managed by an on-chip memory controller. The controller manages the Flash/EE memory as two separate blocks (0 and 1). Block 0 consists of the 32KB Flash/EE memory mapped from 0x0009 0000 to 0x0009 7FFF (including the 2KB kernel space which is reserved at the top of this block) ...
Page 32
... The FEExCON will always read 0x07 immediately after execution of any of these commands. completed, the Flash/EE page or byte may be corrupted. The following sections describe in detail the bit designations of each of Flash/EE control MMRs Table 11: Command Codes in FEE0CON and FEE1CON Rev. PrD | Page 32 of 128 ADuC7032 ...
Page 33
... Table 12: FEE0STA and FEE1STA MMR bit designations FEE0DAT and FEE1DAT Registers: Name : Address : Default Value : Access : Function : Rev. PrD | Page 33 of 128 ADuC7032 // Mass-Erase command //Wait for command to finish FEE0DAT and FEE1DAT 0xFFFF0E0C and 0xFFFF0E8C Non Zero Read/Write Access This 16-bit register contains the data either read from written to the Flash/EE memory ...
Page 34
... As with Block0, FEE1PRO register mirrors the bit definitions of the FEE1HID MMR. The FEE1PRO MMR is allows user code to lock the protection or security configuration of the Flash memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. Rev. PrD | Page 34 of 128 ADuC7032 ...
Page 35
... When cleared by user code these bits will write protect pages 0-119 of the 64KB Flash/EE code memory. Each bit write protects 2 pages and each pages consists of 512 bytes. Table 14: FEE0HID and FEE0PRO MMR bit designations Table 15: FEE1HID and FEE1PRO MMR bit designations Rev. PrD | Page 35 of 128 ADuC7032 ...
Page 36
... Flash/EE memory is reprogrammed. Also note that retention lifetime, based on an activation energy of 0.6 eV, derates with T as shown in Figure 12. 600 450 300 150 JUNCTION TEMPERATURE (°C) Figure 12. Flash/EE Memory Data Retention Rev. PrD | Page 36 of 128 ADuC7032 100 125 135 150 ...
Page 37
... FLASH/EE command. The Abort operation will typically take 10 clock cycles. If the abort operation is not feasible possible to run FLASH/EE programming code and the relevant interrupt routines from SRAM, allowing the core to service the Interrupt immediately. Rev. PrD | Page 37 of 128 ADuC7032 Dead Data access time 1 2 ...
Page 38
... SYSSER1, as described in Table 85. For the duration of Kernel execution, the Watchdog Timer is active with a timeout period of 30ms. This ensures that if an error occurs in the Kernel, the ADuC7032 will be reset. After any reset, the Watchdog timer is disabled once the Kernel code is exited. Normal Kernel execution time, excluding LIN Download, is approximately 5ms ...
Page 39
... LIN COMMAND INITIALIZE ON-CHIP PERIPHERALS TO FACTORY CALIBRATED STATE NO YES JTAG MODE? NTRST = 1 NO YES KEY PRESENT? 0x14 = 0x27011970 NO CHECKSUM PRESENT? 0x14 = CHECKSUM NO FLAG PAGE 0 ERROR NO YES RESET COMMAND Figure 13: ADuC7032 Kernel Flowchart Rev. PrD | Page 39 of 128 ADuC7032 EXECUTE USER CODE ...
Page 40
... The Memory Mapped Register (MMR) space is mapped into the top 4kBytes of the MCU memory space and accessed by indirect addressing, load and store commands, through the ARM7 banked registers. An outline of the ADuC7032s Memory Mapped Register Bank is shown in Figure 14. The MMR space provides an interface between the CPU and all on-chip peripherals ...
Page 41
... W 0xFF Rev. PrD | Page 41 of 128 ADuC7032 Description Active IRQ Source Current State of all IRQ sources ( Enabled and Disabled ) Enabled IRQ sources MMR used to disabled IRQ Sources Software Interrupt Configuration MMR Active IRQ Source Current State of all IRQ sources ( Enabled and Disabled ) ...
Page 42
... Current/Voltage Result FIFO Current ADC Offset MMR Voltage ADC Offset MMR Temperature ADC Offset MMR Current ADC Gain MMR Voltage ADC Gain MMR Temperature ADC Gain MMR Current ADC Result Count Limit Current ADC Result Count Value Current ADC Result Threshold ADuC7032 ...
Page 43
... W 0x000000XX 94 Rev. PrD | Page 43 of 128 ADuC7032 Current ADC Result Threshold Count Limit Current ADC Result Threshold Count Limit Value Current ADC Result Accumulator Current ADC Result Accumulator Threshold Low Power Mode Voltage Reference Scaling Factor UART Transmit Register ...
Page 44
... Flash/EE Control MMR Flash/EE Data MMR Flash/EE Address MMR Flash/EE LFSR MMR Flash/EE Protection MMR Flash/EE Protection MMR Flash/EE Status MMR Flash/EE Control MMR Flash/EE Control MMR Flash/EE Data MMR Flash/EE Address MMR Flash/EE LFSR MMR Flash/EE Protection MMR Flash/EE Protection MMR ADuC7032 ...
Page 45
... Preliminary Technical Data 16-BIT ANALOG TO DIGITAL CONVERTERS The ADuC7032 incorporates three independent sigma-delta ADCs namely, the Current Channel ADC (I-ADC), the Voltage Channel ADC (V-ADC) and the Temperature Channel ADC (T-ADC). These precision measurement channels integrate on- chip buffering, programmable gain amplifier, 16-bit sigma- ...
Page 46
... BY THE MODULATOR. THE UPDATE RATE AND BANDWIDTH OF THIS FILTER ARE PROGRAMMABLE VIA THE ADCFLT MMR FINAL (16-BIT) ADC RESULT Figure 16 : Voltage/ Temperature ADC, Top Level Overview Rev. PrD | Page 46 of 128 ADuC7032 SIGMA-DELTA ADC THE SIGMA-DELTA ARCHITECTURE ENSURES 16 BITS NO MISSING CODES. OUTPUT AVERAGE ...
Page 47
... Preliminary Technical Data ADC GROUND SWITCH The ADuC7032 features an integrated ground switch pin, GND_SW located on Pin15. This switch allows the user to dynamically disconnect ground from external devices. It allows either a direct connection to ground connection to ground via a 20k , this additional resistor may be used to reduce the number of external components required for an NTC circuit ...
Page 48
... Rate 0xBF1D 4Hz 0x961F 10Hz 0x0007 1KHz 0x0000 8KHz Rev. PrD | Page 48 of 128 75mV 150mV 300mV (16) (8) (4*) 0.175 0.35 0.7 0.175 0.35 0.7 0.305 0.380 0.7 1.310 1.650 2.520 4.960 8.020 15.0 28.8V ADC Input Range 65 65 180 1600 0-1.2V ADC Input Range 2.8 2.8 7.5 55 ADuC7032 600mV 1.2V (2*) (1*) 2.8 2.8 2.8 2.8 2.8 2.8 7.600 7.600 55.0 55.0 ...
Page 49
... This bit indicates that the absolute value of the Current Channel Accumulator has exceeded the programmed threshold. This bit is cleared by disabling the Accumulator Comparator function in ADCCFG[6, reconfiguring the ADC. 5 Not Used This bit is reserved for future functionality and should not be monitored by user code Table 22 : ADCSTA MMR Bit Designations Rev. PrD | Page 49 of 128 ADuC7032 ...
Page 50
... ADCSTA MMR bit is set by user code to a ‘1’ , the respective interrupt is enabled. By default all bits are ‘0’ meaning all ADC interrupt sources are disabled. his bit can only be cleared by software when Rev. PrD | Page 50 of 128 ADuC7032 ...
Page 51
... Current Channel ADC while pre-programmed, factory calibration coefficients (downloaded automatically from internal Flash) should be used for voltage temperature measurements external NTC is used, an ADC Self Calibration should be done on the temperature channel. Table 23 : ADCMDE MMR Bit Designations Rev. PrD | Page 51 of 128 ADuC7032 single ADC ...
Page 52
... External reference inputs divided by 2 (VREF, GND_SW)/2 selected, this allows an external reference up to REG_AVDD 1, 1 (REG_AVDD, AGND) divided by 2 selected Table 24 : ADC0CON MMR Bit Designations Diagnostic, internal short configuration Diagnostic, test voltage for gain settings <= 128 Rev. PrD | Page 52 of 128 ADuC7032 ...
Page 53
... External reference inputs divided by 2 (VREF, GND_SW)/2 selected. This allows an external reference up to REG_AVDD 1, 1 (REG_AVDD, AGND) divided by 2 selected. 3 – 0 Not Used These bits are reserved for future functionality and should be written user code Table 25 : ADC1CON MMR Bit Designations VBAT attenuator selected Shorted Input Rev. PrD | Page 53 of 128 ADuC7032 ...
Page 54
... External reference inputs divided by 2 (VREF, GND_SW)/2 selected. This allows an external reference up to REG_AVDD 1, 1 (REG_AVDD, GND_SW) divided by 2 selected. Used for external temperature sensor measurements. 3 – 0 Not Used This bit is reserved for future functionality and should be written 0 by user code Table 26 : ADC2CON MMR Bit Designations Rev. PrD | Page 54 of 128 ADuC7032 ...
Page 55
... For optimal ADC performance, SF should be increased before AF is used. Table 27 : ADCFLT MMR Bit Designations st order Sinc post filter. The averaging factor can = 1.333 * F NOTCH2 for SF ( other than 126 and 127 ) and AF values please refer to Table 28. ADC Rev. PrD | Page 55 of 128 ADuC7032 where F is the location of the 1 NOTCH NOTCH st ...
Page 56
... Table 29 : Allowable Combinations of SF and AF AF Range 0-31 32-63 64-127 Rev. PrD | Page 56 of 128 F *T ADC Settling 3 512000 [ ADC 512000 ADC 512000 ADC 512000 ADC 512000 2 F ADC 8 to63 ADuC7032 ...
Page 57
... The Voltage and Temperature ADCs will also continue to convert if enabled but again only the last conversion result will be available (intermediate V/T-ADC conversion results are not stored) when the ADC counter interrupt occurs Table 30: ADCCFG MMR Bit Designations Rev. PrD | Page 57 of 128 ADuC7032 ...
Page 58
... ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified. Rev. PrD | Page 58 of 128 ADuC7032 ...
Page 59
... Default Value : Access : Read/Write Function : This 8-bit MMR determines how many cumulative(given values below the threshold will decrement or reset the count to 0) I-ADC conversion result readings above ADC0TH must occur before the I-ADC Comparator Threshold Rev. PrD | Page 59 of 128 ADuC7032 ...
Page 60
... Delay for 200us. 3. Switch the Current ADC, ADC0, into Idle-Mode (ADCMDE = 0x03), keeping ADC0CON unchanged. If the Voltage or Temperature channels are to be used, they should be enabled here. 4. Delay for 1ms 5. Switch ADCMDE to desired mode, e.g. ADC0CON = 0x1. Rev. PrD | Page 60 of 128 ADuC7032 ...
Page 61
... Voltage Reference of the ADC Low Power Mode Voltage Reference via ADCMDE[5]. ADC Sinc3 Digital Filter Response The overall frequency response on all ADuC7032s ADCs is dominated by the low pass filter response of the on-chip Sinc3 digital filters. The Sinc3 filters are used to decimate the ADC sigma-delta modulator output data bit-stream to generate a valid 16-bit data result ...
Page 62
... For example, with the CHOP bit ADCFLT[15] set to 1, increasing the SF value (ADCFLT[6:0]) to 0x1F (31dec) and selecting an AF value (ADCFLT[13:8]) of 0x16 (22dec) results in an ADC through-put of 10Hz. The frequency response in this case is shown in Figure 23. Rev. PrD | Page 62 of 128 ADuC7032 2000 4000 6000 8000 10000 ...
Page 63
... ADCFLT configurations. ADC Mode Normal 0x1D Normal Normal Normal Normal Normal Low Power Low Power Low Power Rev. PrD | Page 63 of 128 ADuC7032 Table 32 : Common ADCFLT Configurations Other SF AF ADCFLT Config 0x3F Chop On 0xBF1D 0x1F 0x16 Chop On ...
Page 64
... In general, the simplest way to use the calibration registers is to let the ADC calculate the values required as part of the ADC automatic calibration modes. Rev. PrD | Page 64 of 128 ADuC7032 Chop on) before returning the ADC ...
Page 65
... ADC DIAGNOSTICS The ADuC7032 features diagnostic capability on all three ADCs. Current ADC Diagnostics The ADuC7032 features the capability to detect Open Circuit conditions on the application board. This is accomplished using the two current sources on IIN+ and IIN-, which is controlled via ADC0CON[14,13]. The use of both the IIN+ and IIN- current sources is shown in Table 33 ...
Page 66
... Preliminary Technical Data Temperature ADC Diagnostics The ADuC7032 features the capability to detect Open Circuit conditions on the Temperature Channel inputs. This is accomplished using the two current sources on VTEMP+ and GND_SW, which is controlled via ADC2CON[14,13]. The use of both the VTEMP+ and GND_SW current sources is shown in Table 34 ...
Page 67
... ENABLE_PSM ENABLE_LVF voltage to guarantee full functionality. A POR flag is set in the RSTSTA MMR to indicate a POR reset event has occurred The ADuC7032also features a PSM, or Power Supply Monitor function. Once enabled via HVCFG0[3], the PSM continuously monitors the voltage at the V 6.0V high voltage IRQ is enabled via IRQ/FIQEN[16], generate a system interrupt ...
Page 68
... Low Power 131kHz oscillator. It should also be noted that the low power oscillator drives both the watchdog and core wake-up timers through a divide by 4 circuit. A detailed block diagram of the ADuC7032 clocking system is shown in Figure 27. EXTERNAL CRYSTAL (OPTIONAL) ...
Page 69
... PLLSTA indicates the presence of an oscillator on the XTAL1 pin, the PLL Lock status, and the PLL Interrupt recommended that before the ADuC7032 is powered down, that the clock source for the PLL is switched to the Low Power 131kHz oscillator to reduce wake up time. The Low Power, Oscillator is always active ...
Page 70
... POWCON Pre-write Key POWKEY1: Name : Address : Default Value : Access : Key: Function : Rev. PrD | Page 70 of 128 ADuC7032 PLLKEY1 0xFFFF0418 0x00000000 Write Only 0x00000055 PLLCON is a keyed register that requires a 32 Bit key value to be written before and after PLLCON. PLLKEY1 is the Post-Write ...
Page 71
... If user code powers down the MCU, a dummy MCU cycle should be included after the power-down command is written to POWCON. Table 37 : POWCON MMR bit designations 20.48 MHz 10.24 MHz 5.12 MHz 2.56 MHz 1.28 MHz 640 kHz 320 kHz 160 kHz Rev. PrD | Page 71 of 128 ADuC7032 48.83ns 97.66ns 195.31ns 390.63ns 781.25ns 1.56µs 3.125µs 6.25µs ...
Page 72
... Preliminary Technical Data ADUC7032 LOW POWER CLOCK CALIBRATION The low power 131kHz oscillator may be calibrated using either the precision 131kHz oscillator external 32.768KHz watch crystal. Two dedicated calibration counters and an oscillator trim register are used to implement this feature. One counter, 9-bits wide, is clocked by the accurate clock oscillator, either the Precision oscillator or external watch crystal ...
Page 73
... Calibration Reset Set to reset the calibration counters and disable the Calibration logic 2 Set to clear OSCVAL1 1 Set to clear OSCVAL0 Calibration Enable 0 Set to begin calibration Cleared to abort calibration Table 38 : OSC0TRM MMR Bit Definition Table 39: OSC0CON MMR Bit Definition Rev. PrD | Page 73 of 128 ADuC7032 ...
Page 74
... Precision Oscillator or the 32.768kHz external crystal. Table 40 : OSC0STA MMR Bit Definition OSC0VAL1 Register : Name : Address : Default Value : Access : Function : Power, 131kHz oscillator.. Rev. PrD | Page 74 of 128 ADuC7032 OSC0VAL1 0xFFFF044C 0x00 Read Access only This 10 bit counter is clocked from the Low ...
Page 75
... Preliminary Technical Data PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 15 interrupt sources on the ADuC7032 which are controlled by the Interrupt Controller. Most interrupts are generated from the on-chip peripherals such as the ADC, UART, etc.. The ARM7TDMI CPU core will only recognize interrupts as one of two types, a normal interrupt request IRQ and a fast interrupt request FIQ ...
Page 76
... IRQSTA/FIQSTA register. TIMER0 TIMER1 TIMER2 TIMER3 LIN H/W FLASH/EE PLL LOCK ADC UART SPI XIRQ TIMER0 TIMER1 TIMER2 TIMER3 LIN H/W FLASH/EE PLL LOCK ADC UART SPI XIRQ Figure 29: Interrupt Structure Rev. PrD | Page 76 of 128 ADuC7032 IRQ FIQ ...
Page 77
... Preliminary Technical Data TIMERS The ADuC7032 features four general purpose Timer/Counters: - Timer0, or Life-Time Timer - Timer1, - Timer2 or Wake-up Timer, - Timer3 or Watchdog Timer. The four timers in their normal mode of operation may either be free-running or periodic free-running mode the counter decrements/increments from the maximum/minimum value until zero/full scale and starts again at the maximum /minimum value ...
Page 78
... Figure 30 : Timer 0 block diagram Timer0 Capture Register : T0CAP Name : Address : 0xFFFF0314 0x00 Default Value : Access : Read Only This is a 16-bit register which holds the 16- Function : bit value captured by an enabled IRQ event. Only available in 16-bit mode. Rev. PrD | Page 78 of 128 ADuC7032 TIMER0 IRQ ...
Page 79
... Only available in 16-bit mode. Table 44 : T0CON MMR Bit Descriptions Timer0 Clear Register : Name : Address : Default Value : Access : Function : (with any value) by user code to refresh(reload) Timer0. Rev. PrD | Page 79 of 128 ADuC7032 T0CLRI 0xFFFF0310 0x0FF Write Only This 16-bit, write-only MMR is written ...
Page 80
... PRESCALER 32-BIT 1, 16, 256, OR 32768 UP/DOWN COUNTER TIMER1 VALUE CAPTURE IRQ[31:0] Figure 31 : Timer 1 Block Diagram Rev. PrD | Page 80 of 128 ADuC7032 T1LD 0xFFFF0320 0x00000 Write Only T1LD bit register which holds the 32 T1CLRI 0xFFFF032C 0xFF Write Only This 32-bit, write-only MMR is written ...
Page 81
... Source clock / 256 1111 Source clock / 32768 Timer1 Control Register : Name : Address : Default Value : Access : Function : operation of Timer1 Table 45 : T1CON MMR Bit Descriptions Rev. PrD | Page 81 of 128 ADuC7032 T1CON 0xFFFF0328 0x0000 Read/Write Only This 32-bit MMR configures the mode of ...
Page 82
... Default Value : Access : Function : current value of Timer2 PRESCALER 1, 16, 256, OR 32768 CORE CLOCK Figure 32 : Timer 2 block diagram Rev. PrD | Page 82 of 128 ADuC7032 T2LD 0xFFFF0340 0x00000 Write Only T2LD bit register which holds the 32 T2CLRI 0xFFFF034C 0xFF Write Only This 32-bit, write-only MMR is written ...
Page 83
... Hr:Min:Sec:Hundredths – 255 hours to 0 hour 3-0 Prescalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 ( This setting should be used in conjunction Timer2 Formats 1,0 and 1,1 ) 1111 Source clock / 32768 Table 46 : T2CON MMR Bit Descriptions Rev. PrD | Page 83 of 128 ADuC7032 ...
Page 84
... Timer3 Value Register : Name : Address : Default Value : Access : Function : currentTimer3 count value. Rev. PrD | Page 84 of 128 ADuC7032 T3LD 0xFFFF0364 Write Once Only This 16-bit MMR holds the Timer3 reload T3VAL 0xFFFF0364 0x03D7 Read Only This 16-bit, read-only MMR holds the ...
Page 85
... Timer3 in watchdog mode to prevent a watchdog timer reset event. This register must be written with a specific value (generated by user code, based on a polynomial equation) to refresh the watchdog timer and prevent a watchdog reset. Table 47 : T3CON MMR Bit Definition Rev. PrD | Page 85 of 128 ADuC7032 ...
Page 86
... Preliminary Technical Data GENERAL PURPOSE I/O The ADuC7032 features 9 General Purpose bi-directional I/O pins (GPIO). In general, many of the GPIO pins have multiple functions which can be configured by user code. By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull up resistor and their sink capability is 0.8mA and they can source 0 ...
Page 87
... LIN Output Pin. Used to read directly from LIN PIN for conformance testing. General Purpose I/O LIN HV Input Pin. Used to directly drive LIN Pin for conformance testing. General Purpose I/O LIN Output Pin General Purpose I/O LIN Input Pin Reserved Reserved Rev. PrD | Page 87 of 128 ADuC7032 ...
Page 88
... This bit is cleared user code to configure the GPIO0 pin as a General Purpose I/O (GPIO) pin This bit is set user code to configure the GPIO0 pin Slave Select I/O for the SPI Port Table 49 : GP0CON MMR Bit Designations Rev. PrD | Page 88 of 128 ADuC7032 ...
Page 89
... This bit is set user code to route the UART TxD (transmit data) to the LIN data pin. This configuration is used in LIN mode. 19-17 Reserved These bits are reserved and should be written user code Table 50 : GP1CON MMR Bit Designations Table 51 : GP2CON MMR Bit Designations Rev. PrD | Page 89 of 128 ADuC7032 ...
Page 90
... This bit is cleared user code to configure the GPIO pin assigned to P0 input. This bit is set user code to configure the GPIO pin assigned to P0 output. 23-21 Reserved These bits are reserved and should be written user code Table 52 : GP0DAT MMR Bit Descriptions Rev. PrD | Page 90 of 128 ADuC7032 ...
Page 91
... This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P1.1. User code should write 0 to this bit. 0 Port 1.0 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P1.0. User code should write 0 to this bit. Table 53 : GP1DAT MMR Bit Descriptions Rev. PrD | Page 91 of 128 ADuC7032 ...
Page 92
... This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.4. User code should write 0 to this bit. 3-2 Reserved These bits are reserved and should be written user code Table 54 :GP2DAT MMR Bit Descriptions Rev. PrD | Page 92 of 128 ADuC7032 ...
Page 93
... This bit is set user code to set the external GPIO0 pin high If user software clears this bit to 0, this will have no effect on the external GPIO0 pin. 15-0 Reserved These bits are reserved and should be written user code Table 55 : GP0SET MMR Bit Descriptions Rev. PrD | Page 93 of 128 ADuC7032 ...
Page 94
... If user software clears this bit to 0, this will have no effect on the external GPIO7 pin. 15-0 Reserved These bits are reserved and should be written user code Table 56 : GP1SET MMR Bit Descriptions Table 57 : GP2SET MMR Bit Descriptions Rev. PrD | Page 94 of 128 ADuC7032 ...
Page 95
... If user software clears this bit to 0, this will have no effect on the external GPIO5 pin. 15-0 Reserved These bits are reserved and should be written user code Table 58 : GP0CLR MMR Bit Descriptions Table 59 : GP1CLR MMR Bit Descriptions Rev. PrD | Page 95 of 128 ADuC7032 ...
Page 96
... This bit is set user code to clear the external GPIO7 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO7 pin. 15-0 Reserved These bits are reserved and should be written user code Table 60 : GP2CLR MMR Bit Descriptions Rev. PrD | Page 96 of 128 ADuC7032 ...
Page 97
... Preliminary Technical Data HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE The ADuC7032 integrates a number of high voltage circuit functions which are controlled and monitored via a registered interface consisting of 2 MMRs, namely, HVCON and HVDAT. The HVCON register acts as a command byte interpreter allowing the microcontroller to indirectly read or write 8-bit data(the value in HVDAT) from/to one of 4 High voltage status/configuration registers ...
Page 98
... BUSY = 1, High voltage interface is busy and has not completed the previous command written to HVCON. Bit 1 and bit 2 are not valid. BUSY = 0, High voltage interface is not busy and has completed the command written to HVCON. Bit 1 and bit 2 are valid. Table 61: HVCON MMR Write Bit Designations Table 62: HVCON MMR Read Bit Designations Rev. PrD | Page 98 of 128 ADuC7032 ...
Page 99
... Read back high voltage status register HVMON into HVDAT 0x08 Write the value in HVDAT to the high voltage register HVCFG0 0x09 Write the value in HVDAT to the high voltage register HVCFG1 7-0 High Voltage Data to Read/Write Table 63: HVDAT MMR Bit Designations Rev. PrD | Page 99 of 128 ADuC7032 ...
Page 100
... Read/Write Access : This 8-bit register controls the function of high voltage circuits on the ADuC7032. This register is not an MMR and Function : does not appear in the MMR memory map accessed via the HVCON registered interface. Data to be written to this register is loaded via the HVDAT MMR and data is read back from this register via the HVDAT MMR. ...
Page 101
... Read/Write Access : This 8-bit register controls the function of high voltage circuits on the ADuC7032. This register is not an MMR and Function : does not appear in the MMR memory map accessed via the HVCON registered interface, data to be written to this register is loaded via HVDAT and data is read back from this register via HVDAT. ...
Page 102
... This bit is reserved and should be written user code. 0 Wake Short Circuit Status Flag This bit will be 0 during normal Wake operation This bit will Wake short circuit is detected. Table 66: HVSTA Bit Designations Rev. PrD | Page 102 of 128 ADuC7032 ...
Page 103
... This 8-bit read only register reflects the current status of enabled high voltage related circuits and functions on the Function : ADuC7032. This register is not an MMR and does not appear in the MMR memory map accessed via the HVCON registered interface, and data is read back from this register via HVDAT. ...
Page 104
... The WU pin can be configured in I/O mode by writing HVCFG1[4]. In this mode, a rising or falling edge will immediately generate a high voltage interrupt. HVMON[7] directly reflects the state of the external WU pin. This comparator has a trip level of 3V Rev. PrD | Page 104 of 128 ADuC7032 EXTERNAL WU PIN EXTERNAL WAKE BUS EXTERNAL ...
Page 105
... HVDAT register. During this time the BUSY bit in HVCON[0] is set to indicate the transfer is in progress LOW VOLTAGE FLAG ( LVF ) The ADuC7032 features a Low Voltage flag, which when enabled allows the user to monitor REG_DVDD. When enabled via HVCFG0[2], the Low Voltage Flag may be monitored via HVMON[3] ...
Page 106
... Preliminary Datasheet UART SERIAL INTERFACE The ADuC7032 features a 16450 compatible UART. The UART is a full-duplex Universal Asynchronous Receiver/Transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider, which facilitates high accuracy baud rate generation, and a network addressable mode ...
Page 107
... UART operates. UART Divisor Latch Register 1: Name : COMDIV1 0xFFFF0704 Address : 0x00 Default Value : Access : Read/Write Function : This 8-bit register contains the most significant byte of the divisor latch witch controls the baud rate at which the UART operates. Rev. PrD | Page 107 of 128 ADuC7032 ...
Page 108
... The receiver checks the first Stop bit only, regardless of the number of Stop bits selected Cleared by user to generate 1 Stop bit in the transmitted data 1-0 WLS Word length select bits bits bits bits Table 71 : COMCON0 MMR Bit Descriptions Rev. PrD | Page 108 of 128 ADuC7032 ...
Page 109
... Cleared by reading COMRX Table 72 : COMCON1 MMR Bit Descriptions RxD driven by LIN Input Required for LIN Communications via LIN pin Reserved RxD driven by GP5 Required for Serial communications via GP5 pin ( RxD ) Reserved Table 73: COMSTA0 MMR Bit Descriptions Rev. PrD | Page 109 of 128 ADuC7032 ...
Page 110
... Table 74 : COMIEN0 MMR Bit Descriptions Table 75 : COMIID0 MMR Bit Descriptions Definition No interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Reserved Rev. PrD | Page 110 of 128 ADuC7032 Clearing operation Read COMSTA0 Read COMRX Write data to COMTX or read COMIID0 ...
Page 111
... COMDIV2 0xFFFF072C Address : Default Value : 0x0000 Read/Write Access : Function : This 16-bit register controls the operation of the ADuC7032’s fractional divider Bit Name Description 15 FBEN Fractional baud rate generator enable bit Set by user to enable the fractional baudrate generator Cleared by user to generate baudrate using the standard 450 UART baudrate generator ...
Page 112
... Preliminary Technical Data SERIAL PERIPHERAL INTERFACE The ADuC7032 features a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface which allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. The SPI interface is only operational with core clock divider bits (POWCON[2:0 ...
Page 113
... Cleared by user, the serial clock pulses eat end of each serial bit transfer 1 Master mode enable bit Set by user to enable master mode Cleared by user to enable slave mode 0 SPI enable bit Set by user to enable the SPI Cleared to disable the SPI Table 79 : SPICON MMR Bit Descriptions Rev. PrD | Page 113 of 128 ADuC7032 ...
Page 114
... Address : Default Value : Access : Function : the Serial Peripheral Interface is operating at. For more information on the calculation of the baud rate, please refer to Equation 3 : SPI Baud Rate Calculation. Rev. PrD | Page 114 of 128 ADuC7032 SPIDIV 0xFFFF0A0C 0x1B Read/Write The 8-bit MMR represents the frequency of ...
Page 115
... Preliminary Technical Data LIN (LOCAL INTERCONNECT NETWORK ) INTERFACE The ADuC7032 features a high voltage physical interface between the ARM7 MCU core and an external LIN bus. The LIN interface operates as a slave only interface, operating from 1-20KBaud, and is compatible with the LIN2.0 standard. The pull-up resistor required for a slave node is on-chip, reducing the need for external circuitry ...
Page 116
... Name : LHSSTA 0xFFFF0780 Address : Default Value : 0x00 Read Only Access : The LHS Status register is an 8-bit register whose bits reflect the current operating status of the ADuC7032 LIN Function : interface. Bit Description Reserved These read-only bits are reserved for future use ...
Page 117
... This bit is set user code to clear the internal edge counters in the LHS peripheral, this bit does not reset to 0 automatically and requires user code to write 0 to re-enable the edge counters. Table 82 : LHSCON0 MMR Bit Descriptions Rev. PrD | Page 117 of 128 ADuC7032 ...
Page 118
... In LIN mode, the value read by user code from the LHSVAL0 register can be used calculate the master LIN baud-rate. This calculation can then be used to configure the internal UART baud-rate to ensure correct LIN communication via the UART from the ADuC7032 slave to the LIN master node. Table 83 : LHSCON1 MMR Bit Descriptions Rev ...
Page 119
... LIN based transmissions and receptions. 8T BIT BIT > BIT BIT BIT BIT BIT STA SYNC Figure 39 : LIN Interface Timing Rev. PrD | Page 119 of 128 2T BIT S6 S7 STO PROTECTED ID ADuC7032 ...
Page 120
... As shown in Figure 40, the LIN “break” symbol is used to signal the start of a new frame. It lasts at least 13 bit periods and a slave must be able to detect a “break” symbol, even if it expects data the process of receiving data. The ADuC7032 accomplishes this by using the LHSVAL1 Break Condition and LIN Frame Synchronization Byte The baud rate of the communication via LIN is calculated from the SYNC Byte ...
Page 121
... Under software control it is possible to multiplex the UART data lines (TxD and RxD) to external GPIO pins (GPIO_7 and GPIO_8). For more information please refer to the description of the GPIO Port1 Control Register (GP1CON). Rev. PrD | Page 121 of 128 ADuC7032 STOP BIT6 BIT7 BIT ...
Page 122
... Protected Identifier. The UART must not be ungated, via LHSCON0[8], before the LIN bus returns high. If this occurs, UART communication errors may occur. Example code to ensure this is shown below: This process is shown in detail in Figure 44. Rev. PrD | Page 122 of 128 ADuC7032 ...
Page 123
... GPIO12 must be configured as a GPIO via GP2CON[20]. Once configured, the LIN pin may be pulled high or low via GP2DAT. The ADuC7032 also features short circuit protection on the LIN pin short circuit condition is detected on the LIN pin, HVSTA[2] is set. This bit is cleared by re-enabling the LIN driver via HVCFG1[3] ...
Page 124
... Preliminary Technical Data ADUC7032 ON-CHIP DIAGNOSTICS The ADuC7032 integrates multiple diagnostic support circuits on-chip. These circuits allow the device to test core digital functionality, analog front-end and high-voltage I/O ports in-circuit. ADC Diagnostics Internal Test Voltage The current channel can be configured to convert on an internal 8.3mV test voltage . On any gain range the result should be within ± ...
Page 125
... At power-on, this 32-bit register will hold the value of the original manufacturing lot number from which this specific ADuC7032 unit was manufactured (bottom die only). Used in conjunction with SYSSER1, this lot number will allow the full manufacturing history of this part to be traced. ...
Page 126
... SYSSER0 i.e. the manufacturing lot ID, this number is a unique identifier for the part. System Kernel Checksum: Name : SYSCHK Address : 0xFFFF0240 0x00000000(Updated by kernel at power-on) Default Value : Access : Read/Write Function : At power-on, this 32-bit register will hold the kernel checksum Table 85: SYSSER1 MMR Bit Descriptions Rev. PrD | Page 126 of 128 ADuC7032 ...
Page 127
... Others 3-0 ADuC7030 Family ID 0x0 0x1 0x2 0x3 Others Table 86: FEE0ADR System Identification MMR Bit Descriptions Type6 Type6X Type7OP Type8 Type7OP1 Type7M Type7 Type8W Type9 Type8V Reserved ADuC7030 ADuC7031 ADuC7032 ADuC7033 Reserved Rev. PrD | Page 127 of 128 ADuC7032 ...
Page 128
... Figure 45 : 48-Lead, Plastic Quad Flat Pack, (LQFP-48), Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0.45 0.20 0.09 7° 3.5° 12 0° SEATING 0.08 MAX PLANE VIEW A 0.50 COPLANARITY BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BBC Rev. PrD | Page 128 of 128 9.00 BSC PIN 1 7.00 TOP VIEW BSC SQ (PINS DOWN 0.27 0.22 0.17 ADuC7032 PR05986-0-10/06(PrD) ...