ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 70

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7032-8L
SYNCHRONIZATION OF TIMERS ACROSS
ASYNCHRONOUS CLOCK DOMAINS
The block diagram in Figure 30 shows the interface between
user timer MMRs and the core timer blocks. User code can
access all timer MMRs directly, including TxLD, TxVAL,
TxCON, and TxCLRI. Data must then transfer from these
MMRs to the core timers (T0, T1, T2, T3, and T4) within the
timer subsystem. Theses core timers are buffered from the
user MMR interface by the synchronization (SYNC) block.
The principal of the SYNC block is to provide a method that
ensures that data and other required control signals can cross
asynchronous clock domains correctly. An example of asyn-
chronous clock domains is the MCU running on the 10 MHz
core clock, and Timer2 running on the low power oscillator
of 32 kHz.
OSCILLATOR
OSCILLATOR
PRECISION
ARM7TDMI
CORE CLOCK
POWER
CLOCK
AMBA
CORE
XTAL
GPIO
HIGH
LOW
DOMAIN
(F
CORE
)
AMBA
Figure 31. Synchronizer for Signals Crossing Clock Domains
UNSYNCHRONIZED
0
1
2
4
SIGNAL
INTERFACE
T0 REG
T1 REG
T2 REG
T3 REG
T4 REG
Figure 30. Timer Block Diagram
USER
MMR
Rev. A | Page 70 of 120
TARGET_CLOCK
SYNCHRONIZER
FLIP-FLOPS
TIMER BLOCK
As shown in Figure 30, the MMR logic and core timer logic
reside in separate and asynchronous clock domains. Any data
coming from the MMR core clock domain and being passed to
the internal timer domain must be synchronized to the internal
timer clock domain to ensure it is latched correctly into the core
timer clock domain. This is achieved by using two flip-flops, as
shown in Figure 31, to not only synchronize, but also to double
buffer the data and thereby ensure data integrity in the timer
clock domain.
As a result of the synchronization block, while timer control
data is latched almost immediately (with the fast, core clock) in
the MMR clock domain, this data in turn does not reach the
core timer logic for at least two periods of the selected internal
timer domain clock.
SYNC
SYNC
SYNC
SYNC
SYNC
T0
T1
T2
T3
T4
SYNCHRONIZED
CLOCK DOMAIN
LOW POWER
TIMER 2
SIGNAL
T0
T1
T2
T3
T4
T0IRQ
T1IRQ
T2IRQ
T3IRQ
WdRst
T4IRQ