ADUC7032BSTZ-88-RL Analog Devices Inc, ADUC7032BSTZ-88-RL Datasheet - Page 56

• Manufacturer Part Number: ADUC7032BSTZ-88-RL
• Description: Flash 96k ARM7 TRIPLE 16-Bit ADC LIN IC.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-88-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7032-8L
By default, the ADCFLT = 0x0007 configures the ADCs for
a throughput of 1.0 kHz with all other filtering options (chop,
running average, averaging factor, and Sinc3 modify) disabled.
A typical filter response based on this default configuration is
shown in Figure 19.
An additional Sinc3 modify bit (ADCFLT[7]) is also available in
the ADCFLT register. This bit is set by user code to modify the
standard Sinc3 frequency response, increasing the filter stopband
rejection by 5 dB approximate. This is achieved by inserting a
second notch (NOTCH2) at f
is the location of the first notch in the response. There is a slight
increase in ADC noise if this bit is active. Figure 20 shows the
modified 1 kHz filter response when the Sinc3 modify bit is
active. The new notch is clearly visible at 1.33 kHz, as is the
improvement in stopband rejection when compared to the
standard 1 kHz response shown in Figure 19.
–100
–100
Figure 20. Modified Sinc3 Digital Filter Response at f
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
Figure 19. Typical Digital Filter Response at f
0
0
500
500
1000 1500 2000 2500 3000 3500 4000 4500 5000
1000 1500 2000 2500 3000 3500 4000 4500 5000
(ADCFLT = 0x0007)
(ADCFLT = 0x0087)
FREQUENCY (Hz)
FREQUENCY (Hz)
NOTCH2
= 1.333 × f
ADC
NOTCH
= 1.0 kHz
ADC
where f
= 1.0 kHz
NOTCH
Rev. A | Page 56 of 120
In ADC normal power mode, the maximum ADC throughput
rate is 8 kHz, which is configured by setting the SF and AF bits
in the ADCFLT MMR to 0, with all other filtering options disabled.
This results in 0x0000 written to ADCFLT. A typical 8 kHz filter
response, based on these settings, is shown in Figure 21.
A modified version of the 8 kHz filter response can be configured
by setting the running average bit (ADCFLT[14]). This has the
effect of introducing an additional running average-by-2 filter
on all ADC output samples. This further reduces the ADC output
noise, and while maintaining an 8 kHz ADC throughput rate,
the ADC settling time is increased by one full conversion period.
The modified frequency response for this configuration is
shown in Figure 22.
At very low throughput rates, the chop bit in the ADCFLT
register can be enabled to minimize offset errors and, more
importantly, temperature drift in the ADC dc errors. With
CHOP enabled, there are again two primary variables (Sinc3
decimation factor and averaging factor) available to allow the
user to select an optimum filter response, trading off filter
bandwidth against ADC noise.
Figure 21. Typical Digital Filter Response at f
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
Figure 22. Typical Digital Filter Response at f
0
0
2
2
4
4
6
6
(ADCFLT = 0x4000)
8
8
FREQUENCY (kHz)
FREQUENCY (kHz)
10
10
12
12
14
14
ADC
= 8 kHz, (ADCFLT = 0x0000)
16
16
18
18
ADC
20
= 8 kHz,
20
22
22
24
24