PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 94

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F7X7
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
EQUATION 9-3:
TABLE 9-4:
TABLE 9-5:
DS30498C-page 92
0Bh,8Bh,
10Bh,18Bh
0Ch
0Dh
8Ch
8Dh
87h
11h
92h
12h
15h
16h
17h
1Bh
1Ch
1Dh
95h
96h
97h
Legend:
Note
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
Address
Note:
PWM Frequency
1:
Resolution
INTCON
PIR1
PIR2
PIE1
PIE2
TRISC
TMR2
PR2
T2CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
CCPR3L
CCPR3H
CCP3CON
x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
Name
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (F
REGISTERS ASSOCIATED WITH PWM AND TIMER2
PORTC Data Direction Register
Timer2 Module Register
Timer2 Period Register
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
=
PSPIF
PSPIE
OSFIE
OSFIF
Bit 7
GIE
—
—
—
—
log
(1)
(1)
(
log(2)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
F
F
PWM
CMIF
CMIE
PEIE
ADIF
ADIE
OSC
Bit 6
—
—
—
1.22 kHz
0xFF
)
16
10
bits
TMR0IE
CCP1X
CCP2X
CCP3X
LVDIE
LVDIF
RCIF
RCIE
Bit 5
4.88 kHz
0xFF
CCP1Y
CCP2Y
CCP3Y
INT0IE
10
TXIF
TXIE
4
Bit 4
—
—
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000
SSPIF
SSPIE
BCLIE
BCLIF
RBIE
Bit 3
19.53 kHz
9.6.3
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
0xFF
10
1
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
TMR0IF
CCP1IF
CCP1IE
Bit 2
—
—
SETUP FOR PWM OPERATION
78.12 kHz
TMR2IE
TMR2IF
CCP3IF
CCP3IE
0x3F
INT0IF
Bit 1
1
8
OSC
 2004 Microchip Technology Inc.
= 20 MHz)
TMR1IE 0000 0000 0000 0000
CCP2IE 000- 0-00 000- 0-00
TMR1IF 0000 0000 0000 0000
CCP2IF 000- 0-00 000- 0-00
RBIF
Bit 0
156.3 kHz
0x1F
1
7
0000 000x 0000 000u
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOR
Value on:
208.3 kHz
0x17
6.6
Value on
all other
1
Resets