PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 108

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F7X7
10.4.2
The MSSP module functions are enabled by setting
MSSP enable bit, SSPEN (SSPCON<5>).
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
The I
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
• The overflow bit, SSPOV (SSPCON<6>), was set
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
MSSP module, are shown in timing parameter #100
and parameter #101.
DS30498C-page 106
2
C specification, as well as the requirement of the
MOVF
IORLW
ANDLW
MOVWF
Stop bit interrupts enabled
Stop bit interrupts enabled
before the transfer was received.
before the transfer was received.
2
2
2
2
2
2
C Master mode, clock = Oscillator/4 (SSPADD + 1)
C Firmware Controlled Master mode, slave is Idle
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with Start and
C Slave mode (10-bit address), with Start and
2
C Slave mode hardware will always generate an
TRISC, W
0x18
B’11111001’
TRISC
OPERATION
2
C mode, with the SSPEN bit set,
2
C modes to be selected:
; Example for a 40-pin part such as the PIC16F877A
; Ensures <4:3> bits are ‘11’
; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
2
C opera-
10.4.3
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
To ensure proper communication of the I
mode, the TRIS bits (TRISx [SDA, SCL]) correspond-
ing to the I
(TRISx<7:0>) of the port containing the I
(PORTx [SDA, SCL]) are changed in software, during
I
instruction (BSF, BCF), then the I
functioning properly and I
suspend. Do not change any of the TRISx bits (TRIS
bits of the port containing the I
instruction BSF or BCF during I
is absolutely necessary to change the TRISx bits
during communication, the following method can be
used:
10.4.3.1
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
2.
3.
4.
2
C
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
communication
2
SLAVE MODE
C pins must be set to ‘1’. If any TRIS bits
Addressing
using
 2004 Microchip Technology Inc.
2
C communication may
2
a
C communication. If it
2
2
C mode may stop
C pins) using the
Read-Modify-Write
2
C Slave
2
C pins