PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 174

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F7X7
15.2
The PIC16F7X7 differentiates between various kinds of
Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT Reset during normal operation
• WDT Wake-up during Sleep
• Brown-out Reset (BOR)
FIGURE 15-1:
DS30498C-page 172
Note 1:
MCLR/V
CLKI pin
OSC1/
V
PP
Reset
DD
This is the 32 kHz INTRC oscillator. See Section 4.0 “Oscillator Configurations” for more information.
/RE3 pin
INTRC
OST/PWRT
Brown-out
V
Module
DD
(1)
Detect
Detect
WDT
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Rise
OST
PWRT
10-bit Ripple Counter
WDT
Time-out
Reset
11-bit Ripple Counter
BORSEN
BOREN
Power-on Reset
External
Reset
Sleep
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations, as indicated in
Table 15-3. These bits are used in software to
determine the nature of the Reset. Upon a POR, BOR
or wake-up from Sleep, the CPU requires approxi-
mately 5-10 s to become ready for code execution.
This delay runs in parallel with any other timers. See
Table 15-4 for a full description of Reset states of all
registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 15-1.
Enable PWRT
Enable OST
 2004 Microchip Technology Inc.
S
R
Q
Chip_Reset