PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 67

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 5-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings and to Section 16.1 “Read-Modify-
Write Operations” for additional information on
read-modify-write operations.
FIGURE 5-16:
 2004 Microchip Technology Inc.
Port/Peripheral Select
Peripheral Data Out
Data Bus
WR
Port
WR
TRIS
RD
TRIS
Peripheral
OE
RD
Port
Peripheral Input
Note 1: I/O pins have diode protection to V
(3)
2: Port/Peripheral Select signal selects between port
3: Peripheral OE (Output Enable) is only activated if
PORTC and the TRISC Register
data and peripheral output.
Peripheral Select is active.
TRIS Latch
Data Latch
D
D
CK
CK
(2)
Q
Q
Q
Q
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5> PINS
0
1
Q
EN
D
DD
Schmitt
Trigger
and V
V
V
N
P
SS
DD
SS
.
I/O
pin
(1)
FIGURE 5-17:
Port/Peripheral Select
Peripheral Data Out
Data Bus
WR
Port
WR
TRIS
RD
TRIS
Peripheral
OE
RD
Port
SSPl Input
Note 1: I/O pins have diode protection to V
(3)
2: Port/Peripheral Select signal selects between port data
3: Peripheral OE (Output Enable) is only activated if
and peripheral output.
Peripheral Select is active.
TRIS Latch
Data Latch
D
D
CK
CK
(2)
Q
Q
Q
Q
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<4:3> PINS
0
1
PIC16F7X7
Q
SSPSTAT<6>
CKE
EN
D
Schmitt
Trigger
DS30498C-page 65
DD
and V
Vss
0
1
V
N
P
DD
SS
Schmitt
Trigger
with
SMBus
Levels
.
I/O
pin
(1)