PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 143

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When setting up an Asynchronous Reception, follow
these steps:
1.
2.
3.
4.
5.
TABLE 11-8:
 2004 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (see Section 11.1 “AUSART
Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
x = unknown, — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
INTCON
PIR1
RCSTA
RCREG AUSART Receive Data Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
PSPIF
PSPIE
CSRC
SPEN
Bit 7
GIE
(1)
(1)
PEIE
ADIF
ADIE
Bit 6
RX9
TX9
TMR0IE INT0IE
SREN
TXEN
RCIF
RCIE
Bit 5
CREN ADDEN
SYNC
TXIF
TXIE
Bit 4
SSPIE
SSPIF
RBIE
Bit 3
—
6.
7.
8.
9.
10. If using interrupts, ensure that GIE and PEIE
TMR0IF
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
BRGH
FERR
Bit 2
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE is set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
(bits 7 and 6) of the INTCON register are set.
INT0IF
OERR
TRMT
Bit 1
RX9D
TX9D
RBIF
Bit 0
PIC16F7X7
0000 000x
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
POR, BOR
Value on:
DS30498C-page 141
0000 000u
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
all other
Resets