PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 42

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F7X7
4.6.5
The following are three different sequences for
switching the internal RC oscillator frequency:
• Clock before switch: 31.25 kHz
• Clock before switch: One of INTOSC/INTOSC
TABLE 4-3:
DS30498C-page 40
(31.25 kHz)
(31.25 kHz)
Note 1:
Sleep/POR
(IRCF<2:0> = 000)
1. IRCF bits are modified to an INTOSC/INTOSC
2. The clock switching circuitry waits for a falling
3. The clock switching circuitry then waits for eight
4. The IOFS bit is clear to indicate that the clock is
5. Switchover is complete.
postscaler (IRCF<2:0>
1. IRCF
2. The clock switching circuitry waits for a falling
3. The clock switching circuitry then waits for eight
4. Oscillator switchover is complete.
INTRC/
INTRC
INTRC
From
Sleep
Sleep
postscaler frequency.
edge of the current clock, at which point CLKO
is held low.
falling edges of requested clock, after which it
switches CLKO to this new clock source.
unstable and a 4 ms (approx.) delay is started.
Time dependent code should wait for IOFS to
become set.
(IRCF<2:0> = 000).
edge of the current clock, at which point CLKO
is held low.
falling edges of requested clock, after which it
switches CLKO to this new clock source.
Clock Switch
The 5 s-10 s start-up delay is based on a 1 MHz system clock.
CLOCK TRANSITION SEQUENCE
INTOSC/INTOSC
INTOSC/INTOSC
bits
LP, XT, HS
Postscaler
Postscaler
OSCILLATOR DELAY EXAMPLES
EC, RC
EC, RC
T1OSC
INTRC
are
To
000)
modified
32.768 kHz-20 MHz
125 kHz-8 MHz
125 kHz-8 MHz
DC – 20 MHz
DC – 20 MHz
Frequency
32.768 kHz
31.25 kHz
to
INTRC
4 ms (approx.) and
1024 Clock Cycles
Oscillator Delay
CPU Start-up
CPU Start-up
4 ms (approx.)
• Clock before switch: One of INTOSC/INTOSC
4.6.6
Table 4-3 shows the different delays invoked for
various clock switching sequences. It also shows the
delays invoked for POR and wake-up.
postscaler (IRCF<2:0>
1. IRCF bits are modified to a different INTOSC/
2. The clock switching circuitry waits for a falling
3. The clock switching circuitry then waits for
4. The IOFS bit is set.
5. Oscillator switchover is complete.
INTOSC postscaler frequency.
edge of the current clock, at which point CLKO
is held low.
eight falling edges of requested clock, after
which it switches CLKO to this new clock
source.
(1)
(1)
OSCILLATOR DELAY UPON
POWER-UP, WAKE-UP AND CLOCK
SWITCHING
Following a wake-up from Sleep mode
or POR, CPU start-up is invoked to
allow the CPU to become ready for
code execution.
Following a change from INTRC, the
OST count of 1024 cycles must occur.
Refer to Section 4.6.4 “Modifying the
IRCF Bits” for further details.
 2004 Microchip Technology Inc.
000)
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