PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 91

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the
following and is configured by CCPxCON<3:0>:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value is overwritten by the new
captured value.
9.4.1
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
FIGURE 9-1:
9.4.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
9.4.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit,
CCP1IE (PIE1<2>), clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
 2004 Microchip Technology Inc.
RC2/CCP1
Note:
pin
Capture Mode
Edge Detect
Q’s
CCP PIN CONFIGURATION
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
Prescaler
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
1, 4, 16
and
CCP1CON<3:0>
Set Flag bit CCP1IF
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
(PIR1<2>)
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L
9.4.4
There are four prescaler settings specified by bits,
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any Reset will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 9-1:
9.5
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 9-2:
CLRF
MOVLW
MOVWF
RC2/CCP1
Special Event Trigger will:
• clear TMR1H and TMR1L registers
• NOT set interrupt flag bit, TMR1IF (PIR1<0>)
• (for CCP2 only) set the GO/DONE bit (ADCON0<2>)
non-zero
pin
Output Enable
TRISC<2>
CCP1CON
NEW_CAPT_PS
CCP1CON
Compare Mode
CCP PRESCALER
prescaler.
Q
Special Event Trigger
CCP1CON<3:0>
R
S
Mode Select
Output
CHANGING BETWEEN
CAPTURE PRESCALERS
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
;Turn CCP module off
;Load the W reg with
;the new prescaler
;move value and CCP ON
;Load CCP1CON with this
;value
Set Flag bit CCP1IF
PIC16F7X7
Example 9-1
(PIR1<2>)
Match
DS30498C-page 89
CCPR1H CCPR1L
TMR1H
Comparator
shows
TMR1L
the