PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 81

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>), has no effect since the internal clock is
always in sync.
7.3
Timer1 may operate in Asynchronous or Synchronous
mode depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 7-1:
FIGURE 7-2:
 2004 Microchip Technology Inc.
Note: Arrows indicate counter increments.
T1CKI
(Default High)
T1CKI
(Default Low)
Timer1 Operation in Timer Mode
Timer1 Counter Operation
OSC
T1OSO/T1CKI
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
/4. The synchronize control bit, T1SYNC
Set Flag bit
TMR1IF on
Overflow
T1OSI
TIMER1 INCREMENTING EDGE
TIMER1 BLOCK DIAGRAM
TMR1H
T1OSC
TMR1
TMR1L
Oscillator
Enable
T1OSCEN
(1)
Clock
Internal
F
OSC
TMR1ON
/4
On/Off
7.4
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2 when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration during Sleep mode, Timer1 will not
increment even if the external clock is present, since
the synchronization circuit is shut-off. The prescaler,
however, will continue to increment.
TMR1CS
1
0
T1CKPS1:T1CKPS0
Timer1 Operation in Synchronized
Counter Mode
T1SYNC
Prescaler
1, 2, 4, 8
0
1
2
PIC16F7X7
Synchronized
Clock Input
Synchronize
Q Clock
det
DS30498C-page 79