PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 151

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
Bit SREN is a “don’t care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 11-13: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
 2004 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.
AUSART SYNCHRONOUS SLAVE
RECEPTION
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
AUSART Receive Data Register
Baud Rate Generator Register
PSPIF
PSPIE
CSRC
SPEN
Bit 7
GIE
(1)
(1)
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
TMR0IE INT0IE
SREN
TXEN
RCIE
RCIF
Bit 5
CREN
SYNC
TXIE
Bit 4
TXIF
ADDEN
SSPIF
SSPIE
RBIE
Bit 3
—
When setting up a Synchronous Slave Reception,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
TMR0IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
BRGH
FERR
Bit 2
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
INT0IF
OERR
TRMT
Bit 1
RX9D
TX9D
RBIF
Bit 0
PIC16F7X7
0000 000x 0000 000u
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on:
DS30498C-page 149
Value on
all other
Resets