PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 162

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F7X7
12.7
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRESH register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
TABLE 12-2:
DS30498C-page 160
0Bh,8Bh,
10Bh, 18Bh
0Ch
0Dh
8Ch
8Dh
1Eh
1Fh
9Fh
05h
85h
09h
89h
Legend:
Note 1:
Address
Note:
2:
3:
A/D Operation During Sleep
x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
These registers are reserved on the PIC16F737/767 devices.
RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in Sleep, ensure the SLEEP
instruction
instruction that sets the GO/DONE bit.
INTCON
PIR1
PIR2
PIE1
PIE2
ADRESH A/D Result Register High Byte
ADCON0
ADCON1
PORTA
TRISA
PORTE
TRISE
Name
(2)
SUMMARY OF A/D REGISTERS
(2)
PORTA Data Direction Register
PSPIF
PSPIE
ADCS1
OSFIE
OSFIF
ADFM
Bit 7
RA7
GIE
IBF
—
immediately
(1)
(1)
ADCS0
ADCS2 VCFG1
CMIF
CMIE
PEIE
ADIF
ADIE
Bit 6
OBF
RA6
—
TMR0IE
LVDIF
LVDIE
CHS2
RCIF
RCIE
IBOV
follows
Bit 5
RA5
—
PSPMODE
VCFG0
INT0IE
CHS1
TXIE
Bit 4
TXIF
the
RA4
—
—
—
PCFG3
SSPIF
SSPIE
RE3
BCLIF
BCLIE
CHS0 GO/DONE
RBIE
Bit 3
RA3
—
(3)
(3)
12.8
A device Reset forces all registers to their Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The ADRESH register will contain unknown data after
a Power-on Reset.
12.9
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRESH
to the desired location). The appropriate analog input
channel must be selected and an appropriate acquisi-
tion time should pass before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module but will still reset the Timer1 counter.
PORTE Data Direction bits
TMR0IF
CCP1IE
CCP1IF
PCFG2
Bit 2
RA2
RE2
—
—
Effects of a Reset
Use of the CCP Trigger
TMR2IF TMR1IF 0000 0000 0000 0000
TMR2IE TMR1IE 0000 0000 0000 0000
CCP3IE CCP2IE 000- 0-00 000- 0-00
CCP3IF CCP2IF 000- 0-00 000- 0-00
PCFG1
INT0IF
CHS3
Bit 1
RA1
RE1
bits
PCFG0
ADON
Bit 0
RBIF
 2004 Microchip Technology Inc.
RA0
RE0
(CCP2CON<3:0>)
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xx0x 0000 uu0u 0000
1111 1111 1111 1111
---- x000 ---- x000
0000 1111 0000 1111
POR, BOR
0000 000
Value on:
0000 0000
Value on
all other
Resets
be